Access point pictures designated as randomly accessible positions are I pictures or P pictures. Information indicating the decoding sequence (I1, P1, B1, B2, B3, B4, P2, . . . ) of pictures functioning as access points and attribute information (picture_type) indicating whether a picture functions as an access point or is necessary for decoding of the access point following a given access point are recorded on the video information recording medium. Random access is possible even if the GOP interval is lengthened.

A device for coding video data is configured to determine that a current block of video data is coded using an intra prediction mode; add an intra prediction mode of a first neighboring block of the current block to a most probable mode candidate list for the current block; add an intra prediction mode for a second neighboring block of the current block to the most probable mode candidate list for the current block; add an intra prediction mode for a third neighboring block of the current block to the most probable mode candidate list for the current block; and code the current block of video data using an intra prediction mode.

An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

A device for coding video data is configured to determine that a current block of video data is coded using an intra prediction mode; add an intra prediction mode of a first neighboring block of the current block to a most probable mode candidate list for the current block; add an intra prediction mode for a second neighboring block of the current block to the most probable mode candidate list for the current block; add an intra prediction mode for a third neighboring block of the current block to the most probable mode candidate list for the current block; and code the current block of video data using an intra prediction mode.

A method of compositing video signals includes: obtaining at least two video signals to be composited; determining a multiplier point mode corresponding to each of the at least two video signals; performing a byte size adjustment on the at least two video signals respectively according to the multiplier point mode corresponding to each of the at least two video signals; performing a composite modulation on bytes corresponding to the at least two video signals after the byte size adjustment, and outputting composite-modulated data through a target signal interface of an analog-to-digital conversion chip.

A method of compositing video signals includes: obtaining at least two video signals to be composited; determining a multiplier point mode corresponding to each of the at least two video signals; performing a byte size adjustment on the at least two video signals respectively according to the multiplier point mode corresponding to each of the at least two video signals; performing a composite modulation on bytes corresponding to the at least two video signals after the byte size adjustment, and outputting composite-modulated data through a target signal interface of an analog-to-digital conversion chip.

A mechanism is described for facilitating selective skipping of compression cycles in computing devices. A method of embodiments, as described herein, includes facilitating determining a first current output relating to compression of a current set of data to be same as a previous output from compression of a previous set of data, and turning off a compression engine to skip compression of the current set of data.

An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

A device for coding video data is configured to determine that a current block of video data is coded using an intra prediction mode; add an intra prediction mode of a first neighboring block of the current block to a most probable mode candidate list for the current block; add an intra prediction mode for a second neighboring block of the current block to the most probable mode candidate list for the current block; add an intra prediction mode for a third neighboring block of the current block to the most probable mode candidate list for the current block; and code the current block of video data using an intra prediction mode.