A metal base plate is rectangular in plan view, has a joining region set on a front surface, and has a center line, which is parallel to a pair of short sides that face each other, set in a middle interposed between the pair of short sides. A ceramic circuit board includes a ceramic board that is rectangular in plan view, a circuit pattern that is formed on a front surface of the ceramic board and has a semiconductor chip joined thereto, and a metal plate that is formed on a rear surface of the ceramic board and is joined to the joining region by solder. Here, the solder contains voids and is provided with a stress relieving region at one edge portion that is away from the center line. A density of voids included in the stress relieving region is higher than other regions of the solder.

Embodiments of the present invention are directed to an in-situ warpage monitoring system and method for preventing head-in-pillow (HIP) or other potential defect escapes during a solder reflow process. In a non-limiting embodiment of the invention, a product is passed through a reflow oven. The product can include a printed circuit board (PCB). An amount of warpage of the product is measured at one or more monitoring devices positioned along the reflow oven. Each measured amount of warpage is compared to a predetermined warpage limit. The product is sorted into one of a plurality of designated lots based on the comparison. The lots can include a pass lot, a fail lot, and a marginal pass lot.

A method for fabricating an asymmetric printed circuit board with minimized warpage. The method includes determining a first resin area and a second resin area in a stack of printed circuit board layers. The method further includes performing computer modeling to predict a warpage of the printed circuit board layers during a predicted use of the printed circuit board layers. The method further includes determining a first target coefficient of thermal expansion for the first resin area and a second target coefficient of thermal expansion for the second resin area based on the computer modeling. The method further includes differentially curing resin in the first resin area and the second resin area based on the first target coefficient of thermal expansion and the second target coefficient of thermal expansion. The method further includes forming an asymmetric printed circuit board from the stack of printed circuit board layers.

A device for current determination includes a shunt and a device for temperature measurement including a printed circuit board, an evaluation unit and a temperature sensor. The printed circuit board has a milled groove which runs spirally around the temperature sensor, so that the temperature sensor is arranged on a printed circuit board plateau defined by the milled groove and is displaceable in a direction that is parallel to a normal vector of a plane defined by the printed circuit board. When the temperature sensor is displaced relative to the plane of the printed circuit board, a restoring force is brought about between the printed circuit board and the temperature sensor, wherein the shunt includes a resistance region having a substantially flat surface, wherein the device for current determination is arranged in the resistance region on the surface of the shunt in such a way that the temperature sensor is arranged in thermal connection with the resistance region of the shunt, wherein voltage taps are arranged on both sides of the temperature sensor and electrically contact the surface of the shunt in order to detect a potential difference along the resistance region.

According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

An interconnect substrate includes a core layer including a resin layer mainly composed of a non-photosensitive thermosetting resin and a through interconnect extending through the resin layer, the core layer having no reinforcement member contained therein, a first interconnect structure laminated on a first side of the core layer and including first interconnect layers and first insulating layers mainly composed of a photosensitive resin, and a second interconnect structure laminated on a second side of the core layer and including second interconnect layers and a single second insulating layer mainly composed of a photosensitive resin, wherein the first interconnect layers are electrically connected to the second interconnect layers via the through interconnect, wherein the core layer has greater rigidity than the first interconnect structure and the second interconnect structure, and wherein a thickness of the second interconnect structure is greater than a thickness of each of the first insulating layer.

A component carrier includes a stack with at least one electrically conductive layer structure, at least one electrically insulating layer structure, a cavity delimited at a bottom side at least partially by a top side of a stepped metal structure of the at least one electrically conductive layer structure, and a component embedded in the cavity and arranged on the stepped metal structure. A bottom side of the stepped metal structure has a flat surface extending continuously along at least one horizontal direction.

A printed circuit board includes an insulating layer; a recess portion disposed on one surface of the insulating layer; and a circuit layer disposed on the one surface of the insulating layer and including a signal pattern and a ground pattern. At least a portion of the ground pattern covers at least a portion of the recess portion.

A welding quality processing method and device, and a circuit board. The method includes: obtaining warpage data of each circuit board layer in a multi-layer circuit board under a preset welding temperature change curve; performing simulation according to a stacked state of the multi-layer circuit board and the warpage data to generate a warpage level of each region in the multi-layer circuit board in the stacked state; and processing the multi-layer circuit board according to the warpage level.

In a method for manufacturing a circuit board according to an additive manufacturing shaping method, a circuit board manufacturing method and a circuit board manufacturing device that can reduce the influence of thermal stress on a circuit board by reducing the number of heating steps are provided. A circuit board manufacturing method according to the present disclosure includes a board shaping step of laminating and shaping a circuit board having a wiring on a peeling member adhered to a base member, an attachment step of attaching a metal paste contacting the wiring to the circuit board, an electronic component arrangement step of arranging an electronic component on the circuit board to arrange the electronic component and the wiring via the metal paste, and a heating press step of arranging a press member above the circuit board, and causing the peeling member to be easily released from the base member and curing the metal paste by collectively heating the peeling member and the metal paste while pressing the circuit board with the base member and the press member to correct warpage of the circuit board.