A method for attaching two electronics boards, e.g., a testing PCB and a space transformer, comprises rack welding resin prepreg and a mylar film to a testing PCB; laser drilling via holes in the resin prepreg and mylar film such that the holes are aligned on one side of the resin prepreg with connection/capture pads on the testing PCB and aligned (after attachment) on the other side of the resin prepreg with connection capture pads on a space transformer, filling the via holes with sintering paste; applying a pressure treatment to remove air, bubbles, and voids from the sintering paste; removing the mylar film; and using a lamination press cycle to attach a space transformer to the resin prepreg.

Embodiments presented in this disclosure generally relate to techniques for interconnecting integrated circuits. More specifically, embodiments disclosed herein provide a back mounted interposer (BMI) to facilitate interconnecting of integrated circuits. One example apparatus includes an integrated circuit, an interposer, and a circuit board, at least a portion of the circuit board being disposed between the integrated circuit and the interposer, where the circuit board is configured to provide electrical connection between the interposer and the integrated circuit via connection elements on a first surface of the interposer. The apparatus also includes an interface on a second surface of the interposer, the interface being configured to provide signals from the integrated circuit to an electrical component.

A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.

A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

This disclosure relates to speakers and more specifically to an array speaker for distributing music uniformly across a room. A number of audio drivers can be radially distributed within a speaker housing so that an output of the drivers is distributed evenly throughout the room. In some embodiments, the exit geometry of the audio drivers can be configured to bounce off a surface supporting the array speaker to improve the distribution of music throughout the room. The array speaker can include a number of vibration isolation elements distributed within a housing of the array speaker. The vibration isolation elements can be configured reduce the strength of forces generated by a subwoofer of the array speaker.

An interposer for connecting a module to an M.2 socket includes a different form factor connector. The interposer includes an M.2 connector to couple the interposer to the M.2 socket. The M.2 connector is formed to mate with the M.2 socket. The interposer includes a different form factor socket to couple the interposer to the module including the different form factor connector. The different form factor socket is formed to mate with the different form factor connector.

A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.

Provided is a matable electrical connection structure including a female connection member and a male connection member respectively including a plurality of first connection portions and a plurality of second connection portions, and a plurality of matable connection portions configured to detachably couple the female connection member and the male connection member, and respectively and electrically connect the plurality of first connection portions to the plurality of second connection portions, and the matable connection portions include inner conductive materials respectively and electrically connected to the plurality of first connection portions and provided on inner walls of a plurality of insertion holes formed in the female connection member, columns respectively and electrically connected to the plurality of second connection portions and configured to protrude from the male connection member to be inserted into the insertion hole, and elastic fins configured to extend outside the column to elastically contact the inner conductive material, and at least one of the female connection member and the male connection member is divided into a plurality of areas, and the plurality of matable connection portions are disposed to form a group in each of the areas.

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.