Patent classifications
H05K2201/10621
ADD-IN CARD CONNECTOR EDGE FINGER OPTIMIZATION FOR HIGH-SPEED SIGNALING
An add-in card printed circuit board (PCB) includes a body portion and a card edge portion. The body portion includes a circuit trace associated with a high-speed data communication interface. The card edge portion includes contact fingers, and is configured to be inserted into a card edge connector of an information handling system. The contact fingers include a signal contact finger coupled to the circuit trace, and a ground contact finger that is located adjacent to the signal contact finger. The ground contact finger includes a ground via that couples the ground contact finger to a ground plane layer of the add-in card PCB. The ground via is located half way within the body portion and half way within the card edge portion.
Circuit module
A circuit module (100) includes: a substrate (10) including a plurality of inner conductors (2); a first electronic component arranged on one main surface (S1) of the substrate (10); a first resin layer (40) provided on the one main surface (S1) and configured to seal the first electronic component; a plurality of outer electrodes (B1) provided on another main surface (S2) of the substrate (10) and including a ground electrode; a conductor film (50) provided at least on an outer surface of the first resin layer (40) and a side surface (S3) of the substrate (10) and connected to the ground electrode with at least one of the plurality of inner conductors (2) interposed therebetween; and a resin film (60).
Multi-layer ceramic electronic component and circuit board
A multi-layer ceramic electronic component includes: a ceramic body including first and second internal electrodes laminated in a first axis direction, first and second main surfaces facing in the first axis direction, and first and second end surfaces facing in a second axis direction orthogonal to the first axis, the first and second internal electrodes being drawn to those end surfaces; a first external electrode covering the first end surface and extending to the first main surface; and a second external electrode covering the second end surface and extending to the first main surface. Each external electrode includes a first region including a first outermost layer mainly containing tin and extending from the end surface to the first main surface, and a second region free from an outermost layer mainly containing tin and disposed adjacent to the first region in the first axis direction on the end surface.
CONNECTOR
The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).
Add-in card connector edge finger optimization for high-speed signaling
An add-in card printed circuit board (PCB) includes a body portion and a card edge portion. The body portion includes a circuit trace associated with a high-speed data communication interface. The card edge portion includes contact fingers, and is configured to be inserted into a card edge connector of an information handling system. The contact fingers include a signal contact finger coupled to the circuit trace, and a ground contact finger that is located adjacent to the signal contact finger. The ground contact finger includes a ground via that couples the ground contact finger to a ground plane layer of the add-in card PCB. The ground via is located half way within the body portion and half way within the card edge portion.
Electrical connector assembly having hybrid conductive polymer contacts
An electrical connector assembly includes a carrier having an upper surface and a lower surface. The carrier includes a plurality of contact openings therethrough. The electrical connector assembly includes contacts coupled to the carrier and passing through the corresponding contact openings. Each contact has a conductive polymer column extending between an upper mating interface and a lower mating interface. The conductive polymer column includes an inner core manufactured from a first material and an outer shell manufactured from a second material. The second material has a higher electrical conductivity than the first material. The first material has a lower compression set than the second material.
Reflected signal absorption in interconnect
Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect stub. In one instance, a printed circuit board (PCB) assembly may comprise a substrate and an interconnect (such as a via) formed in the substrate to route an electrical signal within the PCB. The interconnect may include a stub formed on the interconnect. At least a portion of the stub may be covered with an absorbing material to at least partially absorb a portion of the electric signal that is reflected by the stub. The absorbing material may be selected such that its dielectric loss tangent is greater than one, for a frequency range of a frequency of the reflected portion of the electric signal. A dielectric constant of the absorbing material may be inversely proportionate to the frequency of the reflected electric signal. Other embodiments may be described and/or claimed.
SOLID STATE SWITCHING DEVICE INCLUDING HEAT SINKS AND CONTROL ELECTRONICS CONSTRUCTION
A solid state switching device, such as a solid state circuit breaker, includes at least one heat sink, a control electronics printed circuit board (PCB), and power electronics. The power electronics are useful to regulate the flow of current from one terminal of the solid state switching device to another terminal. The power electronics can include one or more solid state devices such as FETs, Thyristors, Thyristors+SiC JFET in parallel, IGBTs, and IGCTs. The control PCB can include a variety of circuit elements useful to perform the function of a gate driver useful to activate the solid state device of the power electronics. The control electronics can be positioned laterally to the power electronics and spanning from a heat sink positioned on one side of the power electronics to a heat sink positioned on an opposing side of the power electronics.
INDUCTORS INCLUDING ELECTRICALLY CONDUCTIVE STANDOFFS
An inductor includes a magnetic core, a first winding, a first electrically conductive standoff, and a second electrically conductive standoff. The magnetic core includes opposing first and second outer surfaces separated from each other in a first direction. The first winding has first and second ends, and the first winding is wound around at least a portion of the magnetic core. The first electrically conductive standoff is connected to the first end of the first winding, and the first electrically conductive standoff extends along the magnetic core in the first direction from the first outer surface to the second outer surface. The second electrically conductive standoff is connected to the second end of the first winding, and the second electrically conductive standoff extends along the magnetic core in the first direction from the first outer surface to the second outer surface.
STACKED SCALABLE VOLTAGE REGULATOR MODULE FOR PLATFORM AREA MINIATURIZATION
The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.