A glass wiring substrate includes: a glass substrate 10 including a first surface 10A and a second surface 10B, having a first wiring portion 20 formed on a first surface side, and having a second wiring portion 30 formed on a second surface side; a through hole 40 formed in a region of the glass substrate 10 in which neither the first wiring portion 20 nor the second wiring portion 30 is formed; and a through hole portion 42 formed on an inner wall 41 of the through hole 40, having one end extending to the first wiring portion 20, having another end extending to the second wiring portion 30, and including a hollow portion 43 corresponding to a central portion of the through hole 40, in which a filling member 61 blocking at least a part of the through hole 40 is provided on a region 10C surrounding an edge portion of the through hole 40 of the first surface 10A, and the filling member 61 includes a glass material.

A printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including conductor pads, an underlayer formed on one of the conductor pads of the conductor layer and including a metal different from a metal of the conductor layer, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and has openings exposing the conductor pads, respectively, and a bump formed directly on a first conductor pad of the conductor pads and including a base plating layer formed in a first opening of the openings and a top plating layer formed on the base plating layer such that a metal of the base plating layer is same as the metal of the conductor layer.

A package structure includes: a substrate, where a plurality of welding pads are disposed on a surface of the substrate, each of the plurality of welding pads includes a bottom layer welding pad and a top layer welding pad which are stacked onto one another, and at least two of peripheral surfaces of the top layer welding pad are protruded relative to peripheral surfaces of the bottom layer welding pad; a chip located on the substrate and spaced apart from the substrate; and a plurality of solder balls, where the plurality of solder balls are welded to the substrate and the chip, and the plurality of solder balls wrap the top layer welding pads.

A circuit board including a substrate, a patterned conductive layer, a patterned insulating layer, a conductive terminal, and a dummy terminal is provided. The patterned conductive layer is disposed on the substrate. The patterned insulating layer is disposed on the substrate and at least covers a portion of the patterned conductive layer. The conductive terminal is disposed on the patterned conductive layer and has a first top surface. The dummy terminal is disposed on the patterned conductive layer and has a second top surface. A first height between the first top surface and the substrate is greater than a second height between the second top surface and the substrate.

A fabrication method of a circuit includes drilling holes in a substrate, so as to form a plurality of first opening holes and second opening holes in the substrate. A cover film is attached onto the substrate, so as to cover the first opening holes and the second opening holes. A portion of the cover film covering the first opening holes is removed, so as to expose the first opening holes. The first opening holes are filled.

A landless multilayer circuit board includes a first substrate, a first circuit, at least one connecting pillar, a second substrate, and a second circuit. The second substrate is on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate, wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit. The second circuit is on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

A multilayer wiring board that improves the reliability of connection at a via hole connection portion, and a method for producing the multilayer wiring board. In a multilayer wiring board comprising a plurality of metal wiring layers alternately laminated with insulating layers interposed therebetween are electrically connected to each other via a via hole plated layer, wherein a dissimilar metallic layer, made from material different from that of the metal wiring layers, is interposed between each of the metal wiring layers on the bottom surface of the via hole and the via hole plated layer, and the dissimilar metallic layer interposed between the each of the metal wiring layers on the bottom surface of the via hole and the via hole plated layer is arranged in a concave shape on the surface of the concave portion formed in the metal wiring layer on the bottom surface of the via hole.

Provided is a chemical mechanical polishing composition to be used for forming a circuit board including a resin substrate on which a wiring layer containing copper or a copper alloy is provided, the chemical mechanical polishing composition including: (A) at least one selected from a group consisting of carboxyl group-containing organic acids and salts thereof; (B) a basic compound having a first acid dissociation constant (pKa) of 9 or more; and (C) abrasive grains, wherein the component (A) has a complex stability constant with copper of 5 or less, and wherein the chemical mechanical polishing composition has a pH value of from 1 to 3.

Provided is a chemical mechanical polishing composition to be used for forming a circuit board including a resin substrate on which a wiring layer containing copper or a copper alloy is provided, the chemical mechanical polishing composition including: (A) at least one selected from a group consisting of organic acids and salts thereof; (B) a phosphorus-containing compound; and (C) abrasive grains each having an absolute value of a zeta potential in the composition of 5 mV or more, wherein, when a content of the component (A) in the composition is represented by M.sub.A mass % and a content of the component (B) therein is represented by M.sub.B mass %, a ratio M.sub.A/M.sub.B of the content of the component (A) to the content of the component (B) ranges from 1 to 10, and wherein the chemical mechanical polishing composition has a pH value of from 1 to 3.

Electronic devices and a manufacturing method thereof are provided. The electronic device includes a first substrate having a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. The electronic device includes a first conductive pattern disposed on the first surface, and a side conductive pattern disposed on the side surface and the first surface. The side conductive pattern is electrically connected to the first conductive pattern. The side conductive pattern includes a first side conductive line and a second side conductive line. A first overlapping portion of the first side conductive line and the first conductive pattern has a first length, a second overlapping portion of the second side conductive line and the first conductive pattern has a second length, and the first length is different from the second length.