Embodiments of the present invention are directed to an in-situ warpage monitoring system and method for preventing head-in-pillow (HIP) or other potential defect escapes during a solder reflow process. In a non-limiting embodiment of the invention, a product is passed through a reflow oven. The product can include a printed circuit board (PCB). An amount of warpage of the product is measured at one or more monitoring devices positioned along the reflow oven. Each measured amount of warpage is compared to a predetermined warpage limit. The product is sorted into one of a plurality of designated lots based on the comparison. The lots can include a pass lot, a fail lot, and a marginal pass lot.

The present application discloses a reflow oven and the operation method thereof. The reflow oven can operate in air mode and inert gas mode. The reflow oven comprises a heating zone, a blocked exhaust zone and a cooling zone. The reflow oven further comprises a first pipeline, a second pipeline and a third pipeline. When the reflow oven operates in air mode, external clean air is delivered to the heating zone and is discharged from the heating zone and the blocked exhaust zone. When the reflow oven operates in inert gas mode, an inert gas is delivered from the blocked exhaust zone to the heating zone and is discharged from the heating zone. Satisfying the accurate temperature profiling necessary for reflow processing in the operation atmosphere of air or an inert gas, the reflow oven in the present application can effectively discharge volatile pollutants to reduce the number of follow-up services and maintenances. In addition, the reflow oven in the present application can save the expensive inert gas.

A layered device having two base films, a conductive pattern attached to the first base film facing the second base film and a bonding layer binding the first base film and the second base film together. The bonding layer includes an opening, and the conductive pattern having an exposed portion aligned with the opening in the bonding layer. Further disclosed is a spacer attached to the first base film and the exposed portion of the conductive pattern, wherein the spacer fills at least part of the space created by the opening in the bonding layer. Also disclosed is a method of producing a layered device.

A solder joint, for bonding an electrode of a circuit board to an electrode of an electronic component, that includes: an Sn—Bi-based solder deposited on the electrode of the circuit board; and a solder alloy deposited on the electrode of the electronic component. The Sn—Bi-based solder alloy has a lower melting point than the solder alloy deposited on the electrode of the electronic component. Fine Bi phases in the solder joint each have an area of less than or equal to 0.5 μm.sup.2. Coarse Bi phases in the solder joint each have an area of greater than 0.5 μm.sup.2 and less than or equal to 5 μm.sup.2. A proportion of the fine Bi phases among the fine Bi phases and the coarse Bi phases is greater than or equal to 60%.

The present invention includes a method of making a RF impedance matching device in a photo definable glass ceramic substrate. A ground plane may be used to adjacent to or below the RF Transmission Line in order to prevent parasitic electronic signals, RF signals, differential voltage build up and floating grounds from disrupting and degrading the performance of isolated electronic devices by the fabrication of electrical isolation and ground plane structures on a photo-definable glass substrate.

Embodiments of a thermal compression bonding (TCB) process cooling manifold, a TCB process system, and a method for TCB using the cooling manifold are disclosed. In some embodiments, the cooling manifold comprises a pre-mixing chamber that is separated from a mixing chamber by a baffle. The baffle may comprise at least one concentric pattern formed through the baffle such that the primary cooling fluid in the pre-mixing chamber is substantially evenly distributed to the mixing chamber. The pre-mixing chamber may be coupled to a source of primary cooling fluid. The mixing chamber may have an input configured to accept the primary cooling fluid and an output to output the primary cooling fluid.

A method for applying ink to a printed circuit board to form a pattern, the method may include flooding the printed circuit board with ink, such that the ink advances within edges of the pattern; freezing the ink before the ink exceeds the edges of the pattern; and vibrating the printed circuit board during a vibration period that at least partially overlaps at least one of the flooding and the freezing.

A circuit board includes first circuit substrate and second circuit substrate; first circuit substrate includes: a first base layer arranged on the first circuit layer and a plurality of first conductive bodies on the substrate layer; the first circuit layer includes a hot pressing area and a non-hot pressing area except the hot pressing area. One end of the first conductive body is electrically connected to the hot pressing area and the other end is exposed to the first base layer; second circuit substrate includes: a second base layer, a second base layer arranged on the second circuit layer and a plurality of second conductive bodies; one end of the second conductive body is electrically connected to the second circuit layer, and the other end is exposed on the second base layer; The body is electrically connected to the second conductive body.

Exemplary embodiments of the invention include a method and apparatus for assembling a semiconductor device. The method may include heating the semiconductor device, which comprises a printed circuit card and a packaging laminate, according to a device heating profile to melt solder material located between an array of contact points on the printed circuit card and an array of corresponding contact points on the packaging laminate; and cooling the semiconductor device to solidify the solder material, wherein during at least a portion of the cooling a temperature of the printed circuit card is kept at substantially a same temperature or a higher temperature than a temperature of an electronic module attached to the packaging laminate opposite the corresponding array of contact points.

An example method of flattening a circuit board assembly includes attaching the circuit board assembly to a structure having dimensions that partly enclose a space, where attachment of the circuit board assembly to the structure creates an air-tight seal over the space, and where the structure has at least one port in fluid communication with the space. The method also includes applying vacuum pressure to the space via the at least one port, where the vacuum pressure forces at least part of the circuit board assembly toward the space, and dispensing thermal interface material selectively onto parts of the circuit board assembly while the vacuum pressure is applied.