The present invention provides a method of fabrication and device made by preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide, masking a design layout comprising one or more holes or post to form one or more high surface area capacitive device for monolithic system level integration on a glass substrate.

A method of forming a metallic pattern on a substrate is provided. The method includes applying onto a metallic surface, a chemically surface-activating solution having an activating agent that chemically activates the metallic surface; non-impact printing an etch-resist ink on the activated surface to produce an etch resist mask according to a predetermined pattern, wherein at least one ink component within the etch-resist ink undergoes a chemical reaction with the activated metallic surface to immobilize droplets of the etch-resist ink when hitting the activated surface; performing an etching process to remove unmasked metallic portions that are not covered with the etch resist mask; and removing the etch-resist mask.

A method for designing a layout of a card edge connector and a server a card are provided. The method includes: determining, based on a type of a GND pin of a card edge connector and space between the card edge connector and GND vias, the number of GND vias connected to the GND pin to maximize the number of the GND vias connected to the GND pin; connecting each GND pin to all the GND vias that match with said GND pin to form one signal return path; and minimizing a length of the signal return path by setting all the GND vias that match with said GND pin in close proximity to said GND pin in the signal return path.

The present invention provides a method of fabrication and device made by preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide, masking a design layout comprising one or more holes or post to form one or more high surface area capacitive device for monolithic system level integration on a glass substrate.

A method of forming a metallic pattern on a substrate is provided. The method includes applying onto a metallic surface, a chemically surface-activating solution having an activating agent that chemically activates the metallic surface; non-impact printing an etch-resist ink on the activated surface to produce an etch resist mask according to a predetermined pattern, wherein at least one ink component within the etch-resist ink undergoes a chemical reaction with the activated metallic surface to immobilize droplets of the etch-resist ink when hitting the activated surface; performing an etching process to remove unmasked metallic portions that are not covered with the etch resist mask; and removing the etch-resist mask.

Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.

Object: A plurality of problems of an electromagnetic wave transmissive cover to be installed in an electromagnetic wave irradiation direction of a sensor using an electromagnetic wave are simultaneously eliminated. Resolution means: An electromagnetic wave transmissive cover 1 is a member to be installed in an electromagnetic wave irradiation direction of a millimeter wave radar 100 using an electromagnetic wave, and includes a colored resin member 3, a transparent resin member 5, and a transparent heater film 7. The transparent resin member 5 is provided on an opposite side to the millimeter wave radar 100 of the colored resin member 3. The transparent heater film 7 is provided on the opposite side to the millimeter wave radar 100 of the colored resin member 3, includes a wiring pattern formed by copper plating or etching, and has electromagnetic wave transmissivity.

A method for designing a layout of a card edge connector and a server a card are provided. The method includes: determining, based on a type of a GND pin of a card edge connector and space between the card edge connector and GND vias, the number of GND vias connected to the GND pin to maximize the number of the GND vias connected to the GND pin; connecting each GND pin to all the GND vias that match with said GND pin to form one signal return path; and minimizing a length of the signal return path by setting all the GND vias that match with said GND pin in close proximity to said GND pin in the signal return path.

A method of forming a metallic pattern on a substrate is provided. The method includes applying onto a metallic surface, a chemically surface-activating solution having an activating agent that chemically activates the metallic surface; non-impact printing an etch-resist ink on the activated surface to produce an etch resist mask according to a predetermined pattern, wherein at least one ink component within the etch-resist ink undergoes a chemical reaction with the activated metallic surface to immobilize droplets of the etch-resist ink when hitting the activated surface; performing an etching process to remove unmasked metallic portions that are not covered with the etch resist mask; and removing the etch-resist mask.

Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.