Disclosed herein are unitary printed circuit boards (PCBs) and methods of using them for testing an integrated circuit (IC). In some embodiments, a unitary PCB comprises a main board portion and a flexible PCB portion, which are configured to be detached from each other at a separation location on the unitary PCB. The main board portion comprises a plurality of pads, and the flexible PCB portion comprises a plurality of through-holes, where a layout of the through-holes corresponds to a layout of the plurality of pads. In some embodiments, a method of testing an IC of a device comprises separating the unitary PBC into a main board portion and a flexible PCB portion, attaching the IC to the main board portion, soldering the main board portion to a platform PCB of the device, and attaching the flexible PCB portion to the main board portion.

A printed circuit board includes a first insulating layer having a through hole, and a via disposed to fill the through hole and to be extended to at least one surface of the first insulating layer, wherein the via includes a plating layer having an inner wall part disposed on an inner wall of the through hole and a land part extended from the inner wall part and disposed on the at least one surface of the first insulating layer, and a metal paste layer including metal particles, and filled in the rest of the through hole and disposed on the plating layer.

An integrated electro-optical circuit board comprises a first flexible substrate having a top side and a bottom side, at least one first optical circuit on the bottom side of the first flexible substrate connected to the top surface through a filled via, at least one first metal trace on the top side of the first flexible substrate, an optical adhesive layer connecting the bottom side of the first flexible substrate to a top side of a second flexible substrate, and at least one second metal trace on a bottom side of the second flexible substrate connected by a filled via through the second flexible substrate, the optical adhesive layer, and the first flexible substrate to the at least one first metal trace.

A mounting substrate manufacturing apparatus includes a first FPC-side pressing member 51 configured to press and heat a first mounting component group 31 including one edge side mounting component that is a flexible printed circuit board 13 arranged on one edge in an arrangement direction in which flexible printed circuit boards 13 arranged on an array substrate 11B and thermally press and bond the first mounting component group 31 on the array substrate 11B, and a second FPC-side pressing member 52 arranged next to the first FPC-side pressing member 51 in the arrangement direction and configured to press and heat a second mounting component group 32 including all the flexible printed circuit boards 13 except for the first mounting component group 31 and thermally press and bond the second mounting component group 32 on the array substrate 11B.

A connection FPC 75 includes a plurality of metal wires 750 between a support layer 751 and a covering layer 752, and an exposed region including contacts 753 serving as end portions of the metal wires 750 is exposed from the covering layer 752. A bending-position guide 760 is provided on the surface of the support layer 751 opposite from the surface on which the metal wires 750 are provided. An edge 760a of the bending-position guide 760 serves as a bending line along which the connection FPC 75 is bent and is disposed in a covering-layer projection area E where the covering layer 752 is projected on the support layer 751. The connection FPC 75 is bent at portions of the metal wires 750 covered with the covering layer 752, that is, at reinforced portions.

A package carrier including a flexible substrate, a first build-up structure and a second build-up structure is provided. The flexible substrate has a first surface and a second surface opposite to each other, and has a first opening connected between the first surface and the second surface. The first build-up structure is disposed on the first surface and covers the first opening. The second build-up structure is disposed on the second surface and has a second opening, and the first opening and the second opening are connected to each other to form a chip accommodating cavity together. In addition, a manufacturing method of the package carrier and a chip package structure having the package carrier are also provided.

An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

A manufacturing method of a display device includes: loading, on a stage, a panel assembly including: a display panel drivable to display an image, and first and second printed circuit boards attached to the display panel, end portions of the first and second printed circuit boards overlapping each other; providing a jet of air to the overlapping end portion of the second printed circuit board to raise the overlapping end portion away from and expose the end portion of the first printed circuit board; fixing the raised end portion away from the exposed end portion of the first printed circuit board; pre-processing the exposed end portion of the first printed circuit board; and aligning a distal end of the pre-processed end portion of the first printed circuit board and a distal end of the end portion of the second printed circuit board.

A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions. The PCB may include a set of layers perpendicular to the set of vias. The set of layers may include a signal layer and a ground layer. The ground layer may be located between the set of stub regions and the signal layer. The method may include drilling to remove at least a portion of a stub region of a via of the set of vias. The method may include performing an electrical test to determine whether a sliver of conductive material is included within the via after drilling to remove the at least a portion of the stub region of the via.

An electronic control device includes a housing including a first region in which heat dissipation fins are formed on one side and an electronic component generating the largest amount of heat is in thermal contact with the other side, and a second region in which an electronic component is in thermal contact with the one side and the other side.