A semiconductor device includes: an active layer including a channel which is spaced apart from a substrate and extending in a direction parallel to a surface of the substrate; a gate dielectric layer formed over the active layer; a word line oriented laterally over the gate insulating layer to face the active layer, and including a low work function electrode and a high work function electrode which is parallel to the low work function electrode; and a dielectric capping layer disposed between the high work function electrode and the low work function electrode.

Described are memory devices having a metal silicide, resulting in a low resistance contact. Methods of forming a memory device are described. The methods include forming a metal silicide layer on a semiconductor material layer on a memory stack, the semiconductor material layer having a capacitor side and a bit line side. A capacitor is then formed on the capacitor side of the metal silicide layer, and a bit line is formed on the bit line side of the metal silicide layer.

Embodiments provide a method for fabricating a semiconductor device and the semiconductor device. The method includes: providing a semiconductor substrate having a first region and a second region; forming an initial mask layer on an upper surface of the substrate; patterning the initial mask layer, forming a first pattern mask having a first height on the first region, and forming a second pattern mask having a second height on the second region, where a pattern density of the first pattern mask is greater than a pattern density of the second pattern mask, and the first height is greater than the second height; and etching the substrate based on the first pattern mask and the second pattern mask, transferring a pattern of the first pattern mask to the first region, and transferring a pattern of the second pattern mask to the second region.

The present application provides a semiconductor structure and a forming method thereof. The method of forming the semiconductor structure includes: forming a capacitor base, the capacitor base including a plurality of capacitor switching structures and an isolation layer located between adjacent capacitor switching structures and covering top surfaces of the capacitor switching structures; removing the isolation layer covering the top surfaces of the capacitor switching structures, and exposing the capacitor switching structures; oxidizing a surface of the capacitor base exposing the capacitor switching structures, and forming an oxide layer; and removing the oxide layer, and exposing the capacitor switching structures.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate. A page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line. The bit line is connected to a sense amplifier circuit via a switch circuit. At least one of word lines is selected and a refresh operation is performed to return the voltage of the channel semiconductor layer of the selected word line to the first data retention voltage by controlling voltages applied to the selected word line, the drive control line, the source line, and the bit line and thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer of the memory cell in which the voltage of the channel semiconductor layer is set to the first data retention voltage using the page write operation. The refresh operation is performed, with the switch circuit kept in a nonconducting state, concurrently with a page read operation of reading page data of a first memory cell group belonging to a first page into the sense amplifier circuit.

A P layer 2 having a band shape is on an insulating substrate 1. An N.sup.+ layer 3a connected to a first source line SL1 and an N.sup.+ layer 3b connected to a first bit line are on respective sides of the P layer 2 in a first direction parallel to the insulating substrate. A first gate insulating layer 4a surrounds a portion of the P layer 2 connected to the N.sup.+ layer 3a, and a second gate insulating layer 4b surrounds the P layer 2 connected to the N.sup.+ layer 3b. A first gate conductor layer 5a connected to a first plate line and a second gate conductor layer 5b connected to a second plate line are isolated from each other and cover two respective side surfaces of the first gate insulating layer 4a in a second direction perpendicular to the first direction. A third gate conductor layer 5c connected to a first word line surrounds the second gate insulating layer 4b. These components constitute a dynamic flash memory.

An n.sup.+ layer 3a connected to a source line SL at both ends, an n.sup.+ layer 3b connected to a bit line BL, a first gate insulating layer 4a formed on a semiconductor substrate 1 existing on an insulating film 2, a gate conductor layer 16a connected to a plate line PL, a gate insulating layer 4b formed on the semiconductor substrate, and a second gate conductor layer 5b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.

Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

A DRAM integrated circuit device is described in which at least some of the peripheral circuits associated with the memory arrays are provided on a first substrate. The memory arrays are provided on a second substrate stacked on the first substrate, thus forming a DRAM integrated circuit device on a stacked-substrate assembly. Vias that electrically connect the memory arrays on the second substrate to the peripheral circuits on the first substrate are fabricated using high aspect ratio via fabrication techniques.