A capacitor includes: a bottom electrode; a top electrode over the bottom electrode; a dielectric film between the bottom electrode and the top electrode; and a doped Al.sub.2O.sub.3 film between the top electrode and the dielectric film, wherein the doped Al.sub.2O.sub.3 film includes a first dopant, and an oxide including the same element as the first dopant has a higher dielectric constant than a dielectric constant of Al.sub.2O.sub.3.

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

A method for fabricating a semiconductor device includes providing a substrate; forming a bit line conductive layer on the substrate and a bit line inner capping layer on the bit line conductive layer to form a bit line structure; a bit line structure; forming a bit line spacer capping layer covering the bit line structure; forming a cell contact adjacent to the bit line structure; forming a blanket pad layer on the bit line spacer capping layer and the cell contact; forming a plurality of pad openings along the blanket pad layer and extending to the bit line spacer capping layer and the bit line inner capping layer to turn the blanket pad layer into a plurality of landing pads; and selectively forming a sealing layer to form a plurality of air gaps between the bit line conductive layer and the plurality of landing pads.

The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity; etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity; etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.