The present disclosure is in the field of semiconductor devices, in particular, to a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate with a trench extending in a direction of the substrate; a capacitor fabricated in the trench, the capacitor includes a lower electrode disposed on an inner wall of the trench, a dielectric combination layer disposed on the lower electrode, and an upper electrode disposed on the dielectric combination layer; the dielectric combination layer includes a stacked structure composed of a nitride layer and an oxide layer. The device can increase the capacitance of the capacitor significantly and reduce the occurrence of charge leakage, thereby improving the electrical performance of the semiconductor memory device.

A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10.sup.−4 Ωcm to 1.0×10.sup.4 Ωcm or a sheet resistance in a range from 1.0×10.sup.2Ω/□ to 1.0×10.sup.10Ω/□.

A semiconductor structure includes a substrate, and a plurality of first semiconductor columns, a storage structure, a plurality of transistors and a first protective layer located above the substrate. The plurality of first semiconductor columns are arranged in array in first and second directions. Each first semiconductor column includes a first part and a second part located on same. The second part includes a bottom portion, an intermediate portion and a top portion. The first direction and the second direction intersect with each other and are both parallel to top surface of the substrate. The storage structure surrounds sidewalls of the first parts. The first protective layer surrounds sidewalls of the top portions of the second parts. A channel structure of each transistor is located in the intermediate portion of the second part, and an extending direction of the channel structure is the same as that of the second part.

Provided are a thin film structure, a capacitor including the thin film structure, a semiconductor device including the thin film structure, and a method of manufacturing the thin film structure, in which the thin film structure may include: a first electrode thin film disposed on a substrate and including a first perovskite-based oxide; and a protective film disposed on the first electrode thin film and including a second perovskite-based oxide that is oxygen-deficient and includes a doping element. The thin film structure may prevent the deterioration of conductivity and a crystalline structure of a perovskite-based oxide electrode, which is a lower electrode, even in a high-temperature oxidizing atmosphere for subsequent dielectric film deposition.

A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor.

A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.

A groove is formed in a first semiconductor layer 1, a sidewall of the groove is coated with a first insulating film 2, a first impurity layer 3 and a second impurity layer 4 thereon are disposed in the groove, a second semiconductor layer 7 is disposed on the second impurity layer, a first semiconductor is disposed at the other part, an n.sup.+ layer 6a and an n.sup.+ layer 6c are positioned at respective ends of the second semiconductor layer 7 and connected to a source line SL and a bit line BL, respectively, a first gate insulating layer 8 is formed on the second semiconductor layer 7, and a first gate conductor layer 9 is connected to a word line WL. Voltage applied to the source line SL, a plate line PL connected to the first semiconductor layer 1, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region 12 of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes from the channel region 12.

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top surface of the substrate. At least one transistor contacts the bonding layer. The transistor includes at least one gate structure disposed on and in contact with a bottom surface of a semiconductor layer of the transistor. The semiconductor further includes a capacitor disposed adjacent to the transistor. The capacitor contacts the semiconductor layer of the transistor and extends down into the substrate. The method includes forming at least one transistor and then flipping the transistor. After the transistor has been flipped, the transistor is bonded to a new substrate. An initial substrate of the transistor is removed to expose a semiconductor layer. A capacitor is formed adjacent to the transistor and contacts with the semiconductor layer. A contact node is formed adjacent to the capacitor.

A method of fabricating a semiconductor device. The method includes forming a dummy structure over a substrate, forming conductive features on opposite sides of the dummy gate structure, removing the dummy structure and a portion of the substrate beneath the dummy gate structure to form a trench, and filling the trench with a dielectric material.

A memory device and a method for manufacturing a memory device are provided. The memory device includes: a substrate, and a plurality of first capacitors embedded in the substrate; a plurality of first vertical transistors and a plurality of second vertical transistors, in which the plurality of first vertical transistors and the plurality of second vertical transistors are arranged on the substrate, and in which each of the plurality of first vertical transistors is electrically connected to a respective one of the plurality of first capacitors; and a plurality of second capacitors arranged on the plurality of first vertical transistors and the plurality of second vertical transistors, in which each of the plurality of second capacitors is electrically connected to a respective one of the plurality of second vertical transistors.