A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.

A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.

A memory device is disclosed. The memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. The resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. The access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.

A cross-point memory includes a plurality of memory devices, with each device comprising a memory layer between first and second address lines. In one preferred embodiment, the memory layer comprises an OTS (Ovonic Threshold Switch) film and an antifuse film. In another preferred embodiment, the memory layer comprises an OTS film having a first switch voltage (i.e. forming voltage V.sub.form) greater than all subsequent switch voltages (i.e. threshold voltage V.sub.th). The cross-point memory is preferably a three-dimensional one-time-programmable memory (3D-OTP), including horizontal 3D-OTP and vertical 3D-OTP

An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.