Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A one time programmable non-volatile memory cell includes a storage element. The storage element includes a glass substrate, a buffer layer, a polysilicon layer and a metal layer. The buffer layer is disposed on the glass substrate. The polysilicon layer is disposed on the buffer layer. A P-type doped region and an N-type doped region are formed in the polysilicon layer. The metal layer is contacted with the N-type doped region and the P-type doped region. The metal layer, the N-type doped region and the P-type doped region are collaboratively formed as a diode. When a program action is performed, the first diode is reverse-biased, and the diode is switched from a first storage state to a second storage state. When a read action is performed, the diode is reverse-biased and the diode generates a read current.

A resistive random-access memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. The first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. A first metal layer is connected with the first doped region and the third doped region. A second metal layer is connected with the conductive layer of the first gate structure and the conductive layer of the third gate structure.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a transistor coupled to a first capacitor and a second capacitor in series, respectively. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells, and wherein the logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first capacitor or second capacitor.

In a compact three-dimensional memory (3D-M.sub.C), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the memory devices in the memory array, the overlap portion and the non-overlap portions of the x-line are both highly-conductive; for the decoding device in the above-substrate decoding stage, while the non-overlap portions are still highly-conductive, the overlap portion is semi-conductive.

The above-substrate decoding stage of a compact three-dimensional memory (3D-M.sub.c) could be an intra-level decoding stage, an inter-level decoding stage, or a combination thereof. For the intra-level decoding stage, contact vias can be shared by address-lines in the same memory level; for the inter-level decoding stage, contact vias can be shared by address-lines from different memory levels.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

A device includes a number of irreversibly programmable memory points. Each irreversibly programmable memory point includes a first semiconductor zone and a gate located on the first zone. A conductive area defines the gates of the memory points. First and second semiconductor areas are respectively located on either side of a vertical alignment with the conductive area. The first zones are alternately in contact with the first and second areas.