Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.

A storage device that includes a non-volatile memory is provided. The non-volatile memory includes a control circuitry that is communicatively coupled to a memory block that includes memory cells arranged word lines. The control circuitry is configured to program the memory cells of a selected word line in a plurality of programming loops to store a single bit of data in each memory cell of the selected word line. The programming loops include programming operations and verify operations. The programming operations include applying a programming voltage to the selected word line, and the verify operations include applying a verify voltage to the selected word line. At least one programming loop of the plurality of programming loops further includes a pre-verify operation. The pre-verify operation includes applying a pre-read voltage to the selected word line. The pre-read voltage is less than the verify voltage.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. The electrically conductive layers include an intermetallic alloy of aluminum and at least one metal other than aluminum. Memory openings vertically extend through the alternating stack. Memory opening fill structures are located in a respective one of the memory openings and include a respective vertical semiconductor channel and a respective vertical stack of memory elements.

A semiconductor memory device according to an embodiment includes: a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one and includes a stepped portion in which, a first pillar disposed in the stepped portion, the first pillar extending in a stacking direction of the stacked body; and a second pillar extending in the stacking direction within the stacked body, the second pillar forming a memory cell at each intersection with at least a part of the plurality of first conductive layers. The first pillar has a semiconductor layer or a second conductive layer extending in the stacking direction and serving as a core material of the first pillar, and a second insulating layer covering a side wall of the semiconductor layer or the second conductive layer and serving as a liner layer of the first pillar.

A semiconductor storage device according to an embodiment includes a substrate, an interconnection layer region, a multi-layered body, a semiconductor body, and a columnar part. The multi-layered body has an end portion facing the interconnection layer region as an end portion in the first direction. The columnar part includes a first portion and a second portion, the first portion is at the end portion of the multi-layered body, the second portion is closer to the substrate than the first portion is. The first portion has a center. The second portion has a center. The center of the second portion in a second direction is displaced in the second direction with respect to the center of the first portion in the second direction. The second direction crosses the first direction.

In one embodiment, a semiconductor device includes a stacked film alternately including a plurality of electrode layers and a plurality of insulating layers. The device further includes a first insulator, a charge storage layer, a second insulator and a first semiconductor layer that are disposed in order in the stacked film. The device further includes a plurality of first films disposed between the first insulator and the plurality of insulating layers. Furthermore, at least one of the first films includes a second semiconductor layer.

To provide a highly reliable memory device. A first insulator is formed over a substrate; a second insulator is formed over the first insulator; a third insulator is formed over the second insulator; an opening penetrating the first insulator, the second insulator, and the third insulator is formed; a fourth insulator is formed on the inner side of a side surface of the first insulator, a side surface of the second insulator, and a side surface of the third insulator, in the opening; an oxide semiconductor is formed on the inner side of the fourth insulator; the second insulator is removed; and a conductor is formed between the first insulator and the third insulator; and the fourth insulator is formed by performing, a plurality of times, a cycle including a first step of supplying a gas containing silicon and an oxidizing gas into a chamber where the substrate is placed, a second step of stopping the supply of the gas containing silicon into the chamber; and a third step of generating plasma containing the oxidizing gas in the chamber.

A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.

A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region. Other memory arrays and methods are disclosed.