Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.

A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.

A capacitor structure is described. The capacitor structure includes a substrate; a source/drain region formed in the substrate to form an active area, the active area having an active area width; and at least two gates formed above the substrate. The at least two gates having a gate width. The gate width is configured to be less than the active area width. And, the at least two gates are formed such that the source/drain region is between the two gates to form at least one channel between the two gates.

A capacitor structure is described. A capacitor structure including a substrate; a source/drain region formed in the substrate to form an active area having an active area width; and a plurality of gates formed above the substrate. The source/drain region having a reflection symmetry. Each of the plurality of gates having a gate width. The gate width is configured to be less than said active area width. And, the plurality of gates are formed to have reflection symmetry.

A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions, a first plurality gates, and a second plurality of gates. The plurality of source/drain regions is formed in the substrate. The first and second plurality of gates is formed above the substrate. Each gate of the first and second plurality of gates has a gate width. The gate widths are configured to be less than an active area width and each gate of the first and second plurality of gates is formed between a pair of the source/drain regions of the plurality of source/drain regions. And, each gate of the first plurality of gates is configured to be in line with a corresponding gate of the second plurality of gates to form a head-to-head gate configuration.

An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.

Various embodiments of the present disclosure are directed towards an integrated chip including a well region in a substrate and comprising a first dopant type. A dielectric layer is over the well region. A conductive structure is over the dielectric layer. A first doped region and a second doped region are in the substrate and comprise the first dopant type. The conductive structure is spaced laterally between the first and second doped regions. A depletion enhancement region is in the substrate and is below the well region. The depletion enhancement region comprises a second dopant type different from the first dopant type and buts a bottom of the well region.