A semiconductor device can include first and second conductive layers that can be positioned over a substrate, and at least one dielectric layer between the first and second conductive layers. The at least one dielectric layer can be positioned over at least a portion of the second conductive layer, and the first conductive layer can be positioned over a portion of the least one dielectric layer. The semiconductor device can further include a third conductive layer that can be positioned over the substrate and can be conductively connected to the second conductive layer and the substrate. The third conductive layer includes a fusible link.

A semiconductor device can include first and second conductive layers that can be positioned over a substrate, and at least one dielectric layer between the first and second conductive layers. The at least one dielectric layer can be positioned over at least a portion of the second conductive layer, and the first conductive layer can be positioned over a portion of the least one dielectric layer. The semiconductor device can further include a third conductive layer that can be positioned over the substrate and can be conductively connected to the second conductive layer and the substrate. The third conductive layer includes a fusible link.

A substrate integrated with passive devices and a manufacturing method thereof are provided. The manufacturing method of the substrate integrated with passive devices includes: providing a transparent dielectric layer with first connection vias therein, wherein the transparent dielectric layer includes a first surface and a second surface, which are opposite to each other along a thickness direction of the transparent dielectric layer; integrating the passive devices onto the transparent dielectric layer, wherein the passive devices include at least an inductor, the integrating the passive devices onto the transparent dielectric layer includes: forming first sub-structures on the first surface of the transparent dielectric layer, forming second sub-structures on the second surface, and forming first connection electrodes in the first connection vias, respectively; wherein the first sub-structures, the first connection electrodes and the second sub-structures are connected together to form a coil structure of the inductor.

A substrate integrated with passive devices and a manufacturing method thereof are provided. The manufacturing method of the substrate integrated with passive devices includes: providing a transparent dielectric layer with first connection vias therein, wherein the transparent dielectric layer includes a first surface and a second surface, which are opposite to each other along a thickness direction of the transparent dielectric layer; integrating the passive devices onto the transparent dielectric layer, wherein the passive devices include at least an inductor, the integrating the passive devices onto the transparent dielectric layer includes: forming first sub-structures on the first surface of the transparent dielectric layer, forming second sub-structures on the second surface, and forming first connection electrodes in the first connection vias, respectively; wherein the first sub-structures, the first connection electrodes and the second sub-structures are connected together to form a coil structure of the inductor.

This description relates generally to semiconductor devices. A semiconductor device can include first and second conductive layers that can be positioned over a substrate, and at least one dielectric layer between the first and second conductive layers. The at least one dielectric layer can be positioned over at least a portion of the second conductive layer, and the first conductive layer can be positioned over a portion of the least one dielectric layer. The semiconductor device can further include a third conductive layer that can be positioned over the substrate and can be conductively connected to the second conductive layer and the substrate. The third conductive layer includes a fusible link.

This description relates generally to semiconductor devices. A semiconductor device can include first and second conductive layers that can be positioned over a substrate, and at least one dielectric layer between the first and second conductive layers. The at least one dielectric layer can be positioned over at least a portion of the second conductive layer, and the first conductive layer can be positioned over a portion of the least one dielectric layer. The semiconductor device can further include a third conductive layer that can be positioned over the substrate and can be conductively connected to the second conductive layer and the substrate. The third conductive layer includes a fusible link.

The application discloses a power semiconductor wafer of a high-frequency bridge arm integrated with a single crystal wafer. The power semiconductor wafer comprises a substrate and a device structure area, wherein the device structure area comprises a first switch area, a second switch area and a logic circuit area; a DC+ electrode, a DC electrode and an SW electrode are arranged on the power semiconductor wafer; and the first switch area and the second switch area comprise long-strip-shaped areas parallel to the long edge and are arranged in parallel. Another aspect of the present application further provides a power conversion module, comprising a bridge arm circuit, wherein the bridge arm circuit comprises an outer decoupling capacitor and a power semiconductor wafer, or comprises an outer decoupling capacitor, a laminated decoupling capacitor and a power semiconductor wafer.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device may include: a semiconductor chip; a hybrid interposer connected to the semiconductor chip, the hybrid interposer including a mold material and an interconnection region including a material different from the mold material, wherein the semiconductor chip is on a first surface of the hybrid interposer that faces in a first direction; and a voltage regulator module electrically connected to the semiconductor chip and configured to supply a voltage to the semiconductor chip, the voltage regulator module including an inductor that is within the hybrid interposer.

A module according to this disclosure comprising: a wiring board; a first chip component that has a first electrode portion, a first non-electrode portion, and a second electrode portion and is provided on the wiring board; and a second chip component that has a third electrode portion, a second non-electrode portion, and a fourth electrode portion and is stacked on the first chip component; wherein the second electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion, wherein the second electrode portion is located between the second non-electrode portion and the wiring board.

A high electron mobility transistor comprises a semiconductor layer structure that includes a channel layer and a barrier layer and source and drain contacts on the semiconductor layer structure. A gate contact and a multi-layer passivation structure are provided on the semiconductor layer structure between the source contact and the drain contact. The multi-layer passivation structure comprises at least first and second silicon nitride layers that have different material compositions. A spacer passivation layer is provided on sidewalls of the first and second silicon nitride layers. A material composition of the spacer passivation layer is different than a material composition of at least one of the layers of the multi-layer passivation structure.