A method includes determining an active region pattern density of a first region of an integrated circuit layout based on a total area of each active region in the first region and an area of the first region. The method includes determining an active region pattern density of a second region of the integrated circuit layout based on a total area of each active region in the second region and an area of the second region. The method includes determining an active region pattern density gradient between the first region to the second region. The method includes determining whether the first region or the second region includes a resistive device. The method includes modifying a portion of the resistive device to include an incremental resistor in response to the first region or the second region including the resistive device.

Each of varicaps 50A to 50C configured to be connected in parallel is an MOS capacitor III produced under a common and single process condition. Each of the varicaps 50A to 50C has a conductor layer serving as a second electrode and formed via a capacitance insulating film on a first conductivity-type semiconductor substrate serving as a first electrode, and a second conductivity-type impurity region formed near a surface in proximity to a region of the first conductivity-type semiconductor substrate opposing the conductor layer. Each of the varicaps 50A to 50C is configured such that a capacitance value as a capacitance element between the first conductivity-type semiconductor substrate serving as the first electrode and the conductor layer serving as the second electrode is changed by applying a control voltage to the conductor layer while applying any one of a plurality of types of direct-current voltages having different voltages to the second conductivity-type impurity region.

A variable capacitance device that includes a semiconductor substrate, a redistribution layer disposed on a surface of the semiconductor substrate, and a plurality of terminal electrodes including first and second input/output terminals, a ground terminal and a control voltage application terminal. Moreover, a variable capacitance element section is formed in the redistribution layer from a pair of capacitor electrodes connected to the first and second input/output terminals, respectively, and a ferroelectric thin film disposed between the capacitor electrodes. Further, an ESD protection element is connected between the one of the input/output terminals and the ground terminal is formed on the surface of the semiconductor substrate.

A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.

The invention relates to wireless biotelemetry of low level bioelectric and biosensor signals by directly modulating the backscatter of a resonant circuit. Low level electrical analog or digital signals are directly applied to a resonant circuit containing a voltage-variable capacitor such as a varactor diode, that proportionally shifts the resonant frequency and so amplitude of radiofrequency backscatter in a way that represents analog bioelectric or biosensor waveform data. By strongly driving the resonant circuit with a radiofrequency source, a voltage variable capacitance can be caused to amplify the bio-signal level by a parametric process and so provide sufficient sensitivity to telemeter for low millivolt and microvolt level signals without additional amplification. A feature of the device is its simplicity and that it accomplishes both modulation and preamplification of low level sensor signals by the same variable capacitance circuit which reduces the device size and power consumption.

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

In some embodiments, a capacitor device includes a metal-oxide-metal (MOM) capacitor array and a varactor array configured overlapping with the MOM capacitor array. The MOM capacitor array includes a first MOM capacitor unit. The first MOM capacitor unit includes a first electrode pattern and a second electrode pattern in a first metallization layer. The first electrode pattern includes a plurality of first fingers and a first bus interconnecting the plurality of first fingers. The second electrode pattern includes a plurality of second fingers and a second bus interconnecting the plurality of second fingers. The varactor array includes a first varactor unit. The first varactor unit includes a first electrode contacting region and a second electrode contacting region. The first electrode pattern contacts the first electrode contacting region. The second electrode pattern contacts the second electrode contacting region.

An integrated structure of acoustic wave device and varactor comprises an acoustic wave device and a varactor formed on a first part and a second part of a semiconductor substrate respectively. The acoustic wave device comprises an acoustic wave device upper structure and a first part of a bottom epitaxial structure. The acoustic wave device upper structure is formed on the first part of the bottom epitaxial structure. The varactor comprises a varactor upper structure and a second part of the bottom epitaxial structure. The varactor upper structure is formed on the second part of the bottom epitaxial structure. The integrated structure of the acoustic wave device and the varactor formed on the same semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor and the acoustic wave device.

A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.