Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

A semiconductor structure includes a substrate and a capacitor over the substrate. The capacitor includes a silicide layer over the substrate. The capacitor includes a first dielectric layer over the silicide layer. The capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. The capacitor includes a second dielectric layer over the metal gate structure. The capacitor further includes a conductive structure over the second dielectric layer.

Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor device comprises a semiconductor substrate, a first ohmic contact and a second ohmic contact disposed over the semiconductor substrate, one or more coupling capacitors, and one or more capacitively-coupled field plates disposed over the semiconductor substrate between the first ohmic contact and the second ohmic contact. Each of the capacitively-coupled field plates is capacitively coupled to the first ohmic contact through one of the coupling capacitors, the coupling capacitor having a first terminal electrically connected to the first ohmic contact and a second terminal electrically connected to the capacitively-coupled field plate.

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.

A metal-oxide-semiconductor (MOS) type semiconductor device, comprising a silicon substrate, a first cathode electrode and a second cathode electrode coupled to the silicon substrate and located on distal ends of the silicon substrate, a poly-silicon (Poly-Si) gate proximally located above the silicon substrate and between the first cathode electrode and the second cathode electrode, wherein the Poly-Si gate comprises a first post extending orthogonally relative to the silicon substrate comprising a first doped silicon slab, a second post extending orthogonally relative to the silicon substrate comprising a second doped silicon slab, wherein the second post is positioned so as to create a width between the first post and the second post, an anode electrode coupled to the first post and the second post and extending laterally from the first post to the second post, and a dielectric layer disposed between the first silicon substrate and the second silicon substrate.

The present disclosure provides a chip part. The chip part includes a substrate, a first external electrode, a second external electrode, a capacitor portion, a lower electrode, a capacitive film and an upper electrode. The first external electrode and the second external electrode are disposed on a first main surface of the substrate. The capacitor portion is disposed on the first main surface of the substrate. The lower electrode includes a first body portion and a first peripheral portion integrally drawn out around the capacitor portion from the first body portion. The capacitive film includes a second body portion disposed within the capacitor portion and a second peripheral portion integrally drawn out from the second body portion to the first peripheral portion. The upper electrode is disposed on the capacitive film.