Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers.

Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers.

A semiconductor package includes a substrate, a semiconductor die, metal interconnects, the semiconductor die being mounted to the substrate via the metal interconnects, an inductor mounted to the substrate, a magnetic material encapsulating the semiconductor die, the inductor, and the metal interconnects, the magnetic material including metal particles suspended in a first insulation material, and a second insulation material covering the magnetic material, wherein the second insulation material is substantially free of metal particles.

The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

An SiP module according to an embodiment of the present invention comprises: a substrate; a first integrated chip (IC) embedded in the substrate; and a second IC disposed on one surface of the substrate, wherein the first IC and the second IC are disposed such that at least portions thereof overlap with respect to a first direction extending through the one surface of the substrate and the other surface thereof.

Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including thin film capacitors are disclosed. An example substrate includes a first glass layer, a dielectric layer on the first glass layer, a second glass layer, the first glass layer between the dielectric layer and the second glass layer, and a capacitor in the layer.

In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

A method for preparing a semiconductor structure, and a semiconductor structure are provided. In a prepared first pattern structure, a thickness of a first insulating layer is equal to a thickness of a second insulating layer, and a thickness of a third insulating layer is equal to a thickness of a fourth insulating layer.

Examples are provided that relate to embedding, in a core of a substrate, an electronic component having a thickness less than a thickness of the core. One example provides an electronic device comprising a substrate comprising a core and one or more buildup layers coupled with the core, each buildup layer comprising a metal layer and a dielectric layer. The core comprises a center comprising a plurality of plies, and an additional layer comprising one or more additional plies. The electronic device further comprises an electronic component embedded in at least one of the center or the additional layer of the core. The electronic component comprises a thickness less than a thickness of the core. The electronic device further comprises an integrated circuit die coupled with the substrate and electrically connected to the electronic component.