Integrated capacitor structures are described. In an example, an interconnect structure includes a first layer of conductive material and a second layer of conductive material. The first layer includes a first horizontal portion having a first opening and extending along a first horizontal plane, and a first vertical portion. The second layer includes a second horizontal portion having a second opening and extending along a second horizontal plane, and a second vertical portion. The interconnect structure also includes a dielectric extending along a third horizontal plane between the first and second horizontal portions, and having one or more openings. The first vertical component extends upward from the first horizontal portion, through one opening in the dielectric and the second opening of second layer, and the second vertical component extends downward from the second horizontal portion, through another opening in the dielectric and the first opening of first layer.

A capacitor includes a first electrode, a second electrode spaced apart from the first electrode, a dielectric layer arranged between the first electrode and the second electrode, and an interface layer arranged between the second electrode and the dielectric layer, wherein the interface layer includes a first element, a second element, and a third element, the first element includes aluminum (Al), the second element includes gallium (Ga), and the third element includes oxygen (O).

A capacitor structure is provided. The capacitor structure comprises an upper electrode, a lower electrode including a lower electrode film and a lower interface electrode film, a capacitor dielectric film between the lower electrode and the upper electrode, and an interface blocking film between the lower electrode and the capacitor dielectric film, the interface blocking film being in contact with the capacitor dielectric film and the lower interface electrode film, wherein the interface blocking film includes a first metal oxide containing a first metal element, the lower interface electrode film includes a second conductive metal oxide containing a second metal element different from the first metal element, the capacitor dielectric film does not include the first metal oxide, and a thickness of the lower interface electrode film is greater than that of the interface blocking film.

A capacitor structure and a forming method thereof are provided. The capacitor structure includes a substrate and a bottom electrode composite layer on the substrate. The bottom electrode composite layer includes a first electrode layer and a second electrode layer on the first electrode layer. An oxidation rate of a material of the second electrode layer is lower than an oxidation rate of a material of the first electrode layer. The capacitor structure also includes a dielectric structure layer on the bottom electrode composite layer.

The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect layer disposed on a substrate, where the first electrode bilayer includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the dielectric layer where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a double double Metal Insulator Metal trench capacitor (10) including a basis electrode (12), an insulator layer (16, 20), a second and a third conductive layers (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to the second conductive layer (18), said second conductive layer (18) being flush with or protruding from the opposite second side (8).

Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

A method of making a metal insulator metal (MIM) capacitor includes forming a copper bulk layer in a base layer, wherein the copper bulk layer includes a hillock extending from a top surface thereof. The method further includes depositing an etch stop layer over the base layer and the copper bulk layer. The method further includes depositing an oxide-based dielectric layer over the etch stop layer. The method further includes forming a capacitor over the oxide-based dielectric layer. The method further includes forming a contact extending through the oxide-based dielectric layer and the etch stop layer to contact the copper bulk layer, wherein the forming of the contact removes the hillock.