A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step. The upper surface of the interlayer insulating film and the upper surface of the first metal plug are interlinked via a recessed portion of the interlayer insulating film.

Provided is a method for manufacturing a power storage device in which a crystalline silicon layer including a whisker-like crystalline silicon region is formed as an active material layer over a current collector by a low-pressure CVD method in which heating is performed using a deposition gas containing silicon. The power storage device includes the current collector, a mixed layer formed over the current collector, and the crystalline silicon layer functioning as the active material layer formed over the mixed layer. The crystalline silicon layer includes a crystalline silicon region and a whisker-like crystalline silicon region including a plurality of protrusions which project over the crystalline silicon region. With the protrusions, the surface area of the crystalline silicon layer functioning as the active material layer can be increased,

Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

A finger metal oxide metal capacitor including an outer conducting structure and an inner conducting structure. The outer conducting structure is defined in a plurality of metal layers and a plurality of via layers of an integrated circuit and includes first and second side portions. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. Each of the outer conducting structure and the inner conducting structure includes respective finger sections extending in the plurality of metal layers. Oxide is arranged between the outer conducting structure and the inner conducting structure.

A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step. The upper surface of the interlayer insulating film and the upper surface of the first metal plug are interlinked via a recessed portion of the interlayer insulating film.

Provided is a method for manufacturing a power storage device in which a crystalline silicon layer including a whisker-like crystalline silicon region is formed as an active material layer over a current collector by a low-pressure CVD method in which heating is performed using a deposition gas containing silicon. The power storage device includes the current collector, a mixed layer formed over the current collector, and the crystalline silicon layer functioning as the active material layer formed over the mixed layer. The crystalline silicon layer includes a crystalline silicon region and a whisker-like crystalline silicon region including a plurality of protrusions which project over the crystalline silicon region. With the protrusions, the surface area of the crystalline silicon layer functioning as the active material layer can be increased.

A silicon capacitor may include a silicon substrate having a three-dimensional pattern, and a dielectric thin film disposed over the silicon substrate and having a structure with a crystal gradient form. A manufacturing method of a dielectric thin film capacitor may include etching a silicon substrate to form a three-dimensional pattern, depositing an amorphous thin film on the etched silicon substrate at a temperature below 300 C., and embedding crystalline grains in the deposited amorphous thin film by performing plasma treatment. A manufacturing method of a dielectric thin film capacitor may include etching a silicon substrate to form a three-dimensional pattern, depositing an amorphous thin film on the etched silicon substrate at a temperature below 300 C., and depositing a crystalline layer on the deposited amorphous thin film by performing plasma treatment.

The present application provides a memory device having laterally extending capacitors of different lengths and levels. The memory device includes a semiconductor substrate; a first insulating layer disposed over the semiconductor substrate; a first bottom electrode disposed over the first insulating layer; a first dielectric layer disposed over the first bottom electrode; a first recess extending through the first dielectric layer; a first capacitor dielectric conformal to the first recess and in contact with the first bottom electrode; and a first top electrode disposed within the first recess and surrounded by the first capacitor dielectric, wherein the first capacitor dielectric and the first top electrode extend laterally over the first bottom electrode and the semiconductor substrate.

A capacitor may include a substrate, a first capacitor portion disposed on the substrate, and a second capacitor portion disposed on the first capacitor portion. The first capacitor portion may include a first insulation layer having a plurality of trenches, a first electrode disposed on the first insulation layer and in the plurality of trenches, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

A device comprises a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of printed capacitors stacked on top of each other with an offset between each capacitor along at least one edge of the capacitors; and wherein each printed capacitor includes a plurality of electrically connected capacitors. Each printed capacitor of the plurality of printed capacitors can be a horizontal or a vertical capacitor. Each printed capacitor can include a plurality of capacitor layers, each capacitor layer including a plurality of electrically connected capacitors