A pillar or trench structure in a substrate includes vertical portions and one or more indented cavities in a sidewall between the vertical portions. The indented cavities are partial undercuts substantially traverse to the vertical portions pillar structure, or separate undercuts attached to an anchor. A higher capacitance density is achieved through the layering of multiple conductive contact layers and insulating layers in the undercuts and the vertical portions of the pillar or trench structure.

The present description concerns an electronic device comprising at least two three-dimensional capacitors, each capacitor being surrounded with a trench comprising a gas pocket.

A capacitor component includes a substrate having first and second surfaces opposing each other, a first interlayer disposed on the first surface of the substrate, the first interlayer including a first trench, a first trench capacitor disposed in the first trench, a second interlayer disposed on the second surface of the substrate, the second interlayer including a second trench, a second trench capacitor disposed in the second trench, and a through-via passing through the substrate to connect the first trench capacitor and the second trench capacitor to each other.

Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

A fabrication method is disclosed. The fabrication method includes: forming, on a substrate, a transistor comprising a source, drain, and gate; forming a multi-layer interconnection structure configured to provide electrical connections for the source, drain, and gate, wherein the multi-layer interconnection structure has a plurality of interconnection layers; forming a metal-insulator-metal (MiM) capacitor in the interconnection structure, the MiM capacitor comprising a first electrode, a high-K spacer with a first vertically-extending sidewall and a second vertically-extending sidewall wherein the first vertically-extending sidewall has a vertically extending interface with the first electrode, and a second electrode wherein the second vertically-extending sidewall has a vertically extending interface with the second electrode; forming a first conductive feature that connects to the first electrode; and forming a second conductive feature that connects to the second electrode.

A solid-state device includes a substrate with a stack of constituent thin-film layers that define an arrangement of electrodes and intervening layers. The constituent layers can conform to or follow a non-planar surface of the substrate, thereby providing a 3-D non-planar geometry to the stack. Fabrication employs a common shadow mask moved between lateral positions offset from each other to sequentially form at least some of the layers in the stack, whereby layers with a similar function (e.g., anode, cathode, etc.) can be electrically connected together at respective edge regions. Wiring layers can be coupled to the edge regions for making electrical connection to the respective subset of layers, thereby simplifying the fabrication process. By appropriate selection and deposition of the constituent layers, the multi-layer device can be configured as an energy storage device, an electro-optic device, a sensing device, or any other solid-state device.

Disclosed herein are IC devices with fishbone capacitor structures. An example capacitor structure includes a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode, wherein the first capacitor electrode is a first line with protrusions on a side of the first line, the second capacitor electrode is a second line with protrusions on a first side of the second line and protrusions on a second side of the second line, the third capacitor electrode is a third line with protrusions on a side of the third line, the protrusions on the side of the first line and the protrusions on the first side of the second line form a first interdigitated capacitor structure, and the protrusions on the side of the third line and the protrusions on the second side of the second line form a second interdigitated capacitor structure.

There is provided a semiconductor device capable of improving performance and reliability of a device, by adjusting the arrangement of penetration patterns included in an electrode support for supporting the lower electrode. The semiconductor device includes a plurality of lower electrodes that are aligned with each other on a substrate along a first direction and a second direction different from the first direction, and a first electrode support that supports the lower electrodes, and includes a plurality of first penetration patterns, wherein the first electrode support includes a center region, and an edge region defined along a periphery of the center region, wherein the first penetration patterns include center penetration patterns that are spaced apart by a first interval in the center region, and wherein the first penetration patterns include edge penetration patterns that are spaced apart by a second interval different from the first interval in the edge region.

Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide. In an embodiment a capacitor device includes 10,000 layers of interleaved graphene separated by 9,999 layers of HfO. Odd layers of the graphene are electrically connected to a first terminal and even layers of graphene are electrically connected to a second terminal of the capacitor device.

A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a gate. The method further includes removing a portion of the gate cap and forming a recess in the gate. A remaining portion of the gate forms a first electrode of the capacitor. The method also includes depositing a dielectric on remaining portions of the gate cap and the remaining portion of the gate. The method additionally includes depositing a conductive material on the dielectric. The method further includes removing a portion of the conductive material and portions of the dielectric to expose a remaining portion of the conductive material and a remaining portion of the dielectric. The remaining portion of the conductive material forms a second electrode of the capacitor. The remaining portion of the dielectric forms an insulator of the capacitor.