The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.

A semiconductor device is described herein. The semiconductor device includes a substrate and a collector region in the substrate. The semiconductor device also includes a plurality of emitter regions in the substrate, each of the plurality emitter regions separate from each other, wherein the plurality of emitter regions is disposed in an area bounded by the collector region.

A device includes a bipolar transistor. The bipolar transistor includes: a collector region, a base region, and an emitter region. A first metallization is in contact with the emitter region, a second metallization is in contact with the base region, and a third metallization is in contact with the collector region. A first connection element is coupled to the first metallization and has dimensions, in a plane of the interface between the first metallization and the connection element, greater than dimensions of the first metallization. A second connection element is coupled to the second metallization and passes through spacers, which at least partially cover the second metallization, surrounding the emitter region. A third connection element is coupled to the third metallization and passes through spacers, which at least partially cover the third metallization, surrounding the base region.

The present disclosure relates to semiconductor devices. An example semiconductor device includes a first well region and a second well region isolated from each other by a first device isolation film; an NPN transistor provided by a first collector region formed in the first well region and including first conductivity-type impurities, and a first emitter region formed in the second well region and including the first conductivity-type impurities; a PNP transistor provided by a second emitter region formed in the first well region and including second conductivity-type impurities different from the first conductivity-type, and a second collector region formed in the second well region and including the second conductivity-type impurities; and an NMOS transistor including a source region and a drain region formed in the second well region and including the first conductivity-type impurities, and a gate structure disposed between the source region and the drain region.

A semiconductor device is provided. The semiconductor includes at least one of a well area in a substrate and having a first conductivity-type; impurity-implanted areas in the well, and having a second conductivity-type different from the first conductivity-type and arranged in a first direction, a first fin structure on the impurity-implanted area and having the second conductivity-type, wherein the first fin structure includes first semiconductor patterns and first sacrificial patterns alternately stacked; a first contact on the first fin structure; a first epitaxial pattern on the well area and having the first conductivity-type; and a second contact on the first epitaxial pattern.

Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

Fabrication of a wireless device involves providing a packaging substrate configured to receive a plurality of components, mounting a radio-frequency module on the packaging substrate, the radio-frequency module including a power amplifier including a bipolar transistor having collector, emitter, base and sub-collector regions, the radio-frequency module further including a conductive via positioned within 35 m of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level, and electrically connecting the radio-frequency module to the packaging substrate using a plurality of connectors.

A horizontal current bipolar transistor comprises a substrate of first conductivity type, defining a wafer plane parallel to said substrate; a collector drift region above said substrate, having a second, opposite conductivity type, forming a first metallurgical pn-junction with said substrate; a collector contact region having second conductivity type above said substrate and adjacent to said collector drift region; a base region comprising a sidewall at an acute angle to said wafer plane, having first conductivity type, and forming a second metallurgical pn-junction with said collector drift region; and a buried region having first conductivity type between said substrate and said collector drift region forming a third metallurgical pn-junction with the collector drift region. An intercept between an isometric projection of said base region on said wafer plane and an isometric projection of said buried region on said wafer plane is smaller than said isometric projection of said base region.

In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.