A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

A MOS transistor including a substrate, a conductive having lateral walls, drain and source regions, and spacers having an upper surface such that the spacers are buried in the substrate and are position between the conductive gate and the drain and source regions is provided. The spacers are each cuboid-shaped and have a width that is constant along the spacers height and independent from a height of the conductive gate. A device including the MOS transistor and a method of manufacture for producing a right-hand portion and a left-hand portion of a MOS transistor is also provided.

Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET) formed over an oxide layer formed on a semiconductor substrate, removing at least part of the semiconductor substrate to expose at least a portion of a backside of the oxide layer, applying an interface material to at least a portion of the backside of the oxide layer, removing at least a portion of the interface material to form a trench, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.

Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.

Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET), forming one or more electrical connections to the FET, forming one or more dielectric layers over at least a portion of the electrical connections, and disposing an electrical element at least partially above the one or more dielectric layers, the electrical element being in electrical communication with the FET via the one or more electrical connections. RF device fabrication further involves applying an interface material over at least a portion of the one or more dielectric layers, removing at least a portion of the interface material to form a trench above at least a portion of the electrical element, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity, the electrical element being disposed at least partially within the cavity.

Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.