A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell. The floating body region is surrounded on all sides by gate region and may include a nanosheet FET, a multi-bridge-channel (MBC) FET, a nanoribbon FET or a nanowire FET. The floating body region is configured to have at least first and second stable states.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell. The floating body region is surrounded on all sides by gate region and may include a nanosheet FET, a multi-bridge-channel (MBC) FET, a nanoribbon FET or a nanowire FET. The floating body region is configured to have at least first and second stable states.

Described is a monolithic integrated circuit for use in quantum computing based on single and multiple coupled quantum dot electron- and hole-spin qubits monolithically integrated with the mm-wave spin manipulation and readout circuitry in commercial complementary metal-oxide-semiconductor (CMOS) technology. The integrated circuit includes a plurality of n-channel or p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) cascodes each including a single-spin qubit or two coupled quantum dot qubits formed in an undoped semiconductor film adjacent at least one top gate. There is also a back gate formed in a silicon substrate adjacent a buried oxide layer or the at least one top gate, where the back gate controls the electron or hole entanglement and exchange interaction between the two coupled quantum dot qubits. The monolithic integrated circuits described may be used for monolithically integrated semiconductor quantum processors for quantum information processing.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

The present inventive concept relates to a spin qubit transistor (100) comprising a base layer (102), a first qubit comprising, a first computing semiconductor island (106) and a first readout semiconductor island (108) arranged with a distance in the range of 3-10 nm therebetween, a second qubit comprising, a second computing semiconductor island (110) and a second readout semiconductor island (112) arranged with a distance in the range of 3-10 nm therebetween, wherein each of said semiconductor islands has a size causing each of said semiconductor islands to exhibit 3-dimensional quantum confinement of a single electron hole, and wherein each of said semiconductor islands forms a semiconductor heterojunction with the base layer. Each of the semiconductor islands has a corresponding gate (G1-G4), for modulation of the computing islands or readout of the readout islands. Said first computing semiconductor island and said second computing semiconductor island are configured to have a unique resonance frequency respectively. A control electrode arrangement (B) between the computing and the readout islands controls the coupling between the qubits. The present inventive concept further comprises a method for forming a spin qubit transistor and a quantum computer comprising at least one spin qubit transistor.

Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that have improved negative bias temperature (NBTI) and boosted performance of the PMOS transistor due to the presence of a silicon germanium (SiGe) channel in the PMOS transistor. Specifically, a plurality of nanosheet release layers is removed from the N-channel metal-oxide-semiconductor (NMOS) transistor to form a plurality of openings adjacent the corresponding plurality of nanosheet channel layers, and a plurality of oxide layers are deposited in each of the plurality of openings.

Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that have improved negative bias temperature (NBTI) and boosted performance of the PMOS transistor due to the presence of a silicon germanium (SiGe) channel in the PMOS transistor. Specifically, a plurality of nanosheet release layers is removed from the N-channel metal-oxide-semiconductor (NMOS) transistor to form a plurality of openings adjacent the corresponding plurality of nanosheet channel layers, and a plurality of oxide layers are deposited in each of the plurality of openings.

The invention provides a spin qubit-type semiconductor device capable of achieving both high-speed spin manipulation and high integration, and an integrated circuit for the spin qubit-type semiconductor device. The spin qubit-type semiconductor device includes a body comprised of at least one of a semiconductor layer itself formed with a quantum dot and a structural portion arranged around the semiconductor layer, a gate electrode arranged at a position on the semiconductor layer, which faces the quantum dot, at least one micro magnet wholly or partly embedded in the body so that a first position condition in which the micro magnet is at a position near the quantum dot, a second position condition in which the position of a lower end of the micro magnet is located below the gate electrode, and a third position condition in which when viewed from above the body, the micro magnet is arranged at a position having no rotational symmetry with the quantum dot as the center of rotation are satisfied, and a static magnetic field applying unit capable of applying a static magnetic field to the quantum dot and the micro magnet.

A method of fabricating a quantum-dot structure includes the steps of preparing a semiconductor material layer formed on a substrate; forming an insulating layer from a portion of the semiconductor material layer by oxidizing the semiconductor material layer; and forming quantum dots which are located in the insulating layer and are made of a semiconductor material by diffusing the semiconductor material into the insulating layer by annealing. According to the method of fabricating the quantum-dot structure, it is possible to form the quantum dots made of the semiconductor material from the substrate through self-assembly. According to the method of fabricating the quantum-dot structure, it is possible to form quantum dots and a tunneling structure thereof through self-assembly, and it is possible to fabricate devices such as a single electron transistor based on quantum dots, using processes of existing silicon (Si)-based devices.

An integrated circuit device includes an insulating structure, a first source/drain region on the insulating structure, a second source/drain region on the insulating structure and spaced apart from the first source/drain region, a gate structure including at least one gate electrode layer, the gate structure being between the first source/drain region and the second source/drain region, a contact plug connected to the gate structure, a first backside source/drain contact structure penetrating the insulating structure and connected to the first source/drain region, an electrical insulating layer on a side wall of an end portion of the first backside source/drain contact structure, the electrical insulating layer contacting the first source/drain region, and a first semiconductor material layer on the electrical insulating layer, where the electrical insulating layer is configured to electrically insulate the first semiconductor material layer from the first backside source/drain contact structure.