A semiconductor device includes a backside power delivery network (BSPDN). The semiconductor device includes a substrate, a first active pattern extending in a first direction, on a top surface of the substrate, a second active pattern extending in the first direction, and spaced apart from the first active pattern in a second direction intersecting the first direction, on the top surface of the substrate, a gate structure extending in the second direction, on the first active pattern and the second active pattern, a first source/drain pattern connected to the first active pattern, on a side surface of the gate structure, a second source/drain pattern connected to the second active pattern, on the side surface of the gate structure, back source/drain contacts penetrating the substrate, and a first power line connected to the back source/drain contacts on a bottom surface of the substrate.

Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. For example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. The nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. A dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

A semiconductor device includes: a gate structure having a side in a first direction and extending in a second direction intersecting the first direction; a source/drain region on the side of the gate structure; a plurality of channel layers spaced apart from each other in a third direction intersecting the first direction and the second direction and surrounded by the gate structure; and a plurality of inner spacers between the gate structure and the source/drain region, wherein the plurality of inner spacers have respective heights in the third direction increasing in the third direction toward bottom, and have respective thicknesses in the first direction decreasing in the third direction toward bottom.

A semiconductor device includes channel members vertically stacked, a gate dielectric layer wrapping around each of the channel members, a first work function (WF) layer disposed over the gate dielectric layer and wrapping around each of the channel members, a first WF isolation layer disposed over the first WF layer, a second WF layer disposed over the first WF isolation layer, a second WF isolation layer disposed over the second WF layer, and a metal fill layer disposed over the second WF isolation layer. The first WF layer has a uniform thickness. The second WF isolation layer is a nitride-containing layer.

A method can include receiving a first power supply voltage at a first terminal at a first side of an IC device and providing a row of stacked pairs of insulated gate field effect transistor (IGFETs) substantially at the second side of the IC device. Each stacked pair can include a first and second IGFET of different conductivity types. Each IGFET can include multiple channels and a control gate that substantially surrounds the channels. A first power supply can be coupled from the first power supply terminal to a first source of one IGFET of the stacked pair via a first conductive via disposed between the first side and the second side and a first conductive line buried in and proximate the second side below the row of stacked pairs. Corresponding devices and systems are also disclosed.

An integrated circuit device includes: a fin-type active region on a substrate; a nanosheet disposed on the fin-type active region; a gate line surrounding the nanosheet, wherein the gate line overlaps the nanosheet; a source/drain region disposed on the fin-type active region and contacting the nanosheet; and an interface insulating film surrounding the gate line, and including an inner spacer portion disposed between a sidewall of the gate line and the source/drain region, wherein the inner spacer portion includes: a first inner spacer portion protruding toward the source/drain region, while covering the sidewall of the gate line and while spaced apart from the nanosheet, wherein the first inner spacer portion has a first thickness; and a second inner spacer portion extending from the first inner spacer portion toward the nanosheet, wherein the second inner spacer portion has a second thickness that is less than the first thickness.

A gate-all-around field effect transistor (GAAFET) includes a substrate, a source structure, a drain structure, at least one channel, and a gate structure. The source structure and the drain structure are disposed on the substrate. Each of the at least one channel is extending between the source structure and the drain structure. The gate structure is disposed between the source structure and the drain structure, and surrounding the at least one channel. When the GAAFET is operated in a saturation state, each of the at least one channel comprises a first region, a second region, and an electrical junction between the first region and the second region. The first region is adjacent to the drain structure, and the second region is adjacent to the first region.

A bandgap reference circuit includes a bandgap voltage generator and a detector. The bandgap voltage generator includes an operation amplifier, an input circuit and a load circuit. The detector includes a control circuit and a response circuit. The two input terminals of the operation amplifier are respectively connected with a first node and a second node. An output terminal of the operation amplifier is connected with a bias node. The load circuit is connected with a third node. The input circuit is connected with the first node and the second node. The control circuit activates a sensing signal according to a bias voltage. When the sensing signal is activated, the bias node is connected with a power supply voltage through the response circuit. When the sensing signal is not activated, the bias node is disconnected from the power supply voltage through the response circuit.

A method includes forming a multi-layer stack including a plurality of semiconductor nanostructures. The multi-layer stack includes a semiconductor nanostructure, and a sacrificial semiconductor layer over the semiconductor nanostructure. The method further includes depositing a semiconductor layer over and contacting the semiconductor nanostructure, removing the sacrificial semiconductor layer, and forming a replacement gate stack encircling a combined region of the semiconductor nanostructure and the semiconductor layer.