Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

A semiconductor circuit structure includes a semiconductor substrate with an original semiconductor surface, an active region within the semiconductor substrate, and a transistor formed based on the active region. The transistor includes a gate structure, a first spacer neighboring to a first sidewall of the gate structure, and a second spacer neighboring to a second sidewall of the gate structure. Wherein a thermal conductivity of the first spacer or the second spacer includes is higher than the thermal conductivity of silicon nitride (Si.sub.3N.sub.4).

Provided is a semiconductor device including a power distribution network layer on a lower surface of a substrate, a gate electrode on the substrate, a first source/drain pattern and a second source/drain pattern on the substrate, the first and second source/drain patterns each including a first pattern and a second pattern spaced apart from each other with the gate electrode therebetween, a through via structure penetrating the substrate and extending along a direction perpendicular to an upper surface of the substrate, the through via structure connecting the power distribution network layer and the first pattern of the first source/drain pattern, and a rear surface power via extending from below the second pattern of the first source/drain pattern to below the second pattern of the second source/drain pattern.

A semiconductor device includes a semiconductor substrate, a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a dielectric wall, and a first isolation feature. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure are disposed on the semiconductor substrate. The first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure. The dielectric wall is disposed on the semiconductor substrate and is connected between the first semiconductor structure and the second semiconductor structure. The first isolation feature is disposed between the first semiconductor structure and the third semiconductor structure, and extends into the semiconductor substrate.

A semiconductor device structure and methods of forming the same are described. The structure includes a first semiconductor layer disposed over a substrate, the first semiconductor layer has an edge portion and a center portion, and a height of the center portion is substantially greater than a height of the edge portion. The structure further includes a dielectric spacer disposed below and in contact with the edge portion of the first semiconductor layer, a gate dielectric layer surrounding the center portion of the first semiconductor layer, and a gate electrode layer disposed on the gate dielectric layer surrounding the center portion of the first semiconductor layer.

The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.

Semiconductor devices having nanosheet architectures, e.g., transistors such as horizontal gate-all-around (hGAA) structures, methods, and apparatuses for forming such semiconductor devices are described. The methods comprise forming a cladding material around each of a first plurality of nanosheets; oxidizing a portion of the cladding material to form an oxidize film, such as a silicon oxide (SiO.sub.2) film, around the cladding material and a form a second plurality of nanosheets; annealing the second plurality of nanosheets at a temperature of less than or equal to 850 C.; and removing the oxide film.

An exemplary device includes a frontside power rail disposed over a frontside of a substrate, a backside power rail disposed over a backside of the substrate, an epitaxial source/drain structure disposed between the frontside power rail and the backside power rail. The epitaxial source/drain structure is connected to the frontside power rail by a frontside source/drain contact. The epitaxial source/drain structure is connected to the backside power rail by a backside source/drain via. The backside source/drain via is disposed in a substrate, and a dielectric layer is disposed between the substrate and the backside power rail. The backside source/drain via extends through the dielectric layer and the substrate. A frontside silicide layer may be between the frontside source/drain contact and the epitaxial source/drain structure, and a backside silicide layer may be between the backside source/drain contact and the epitaxial source/drain structure, such that the epitaxial source/drain structure between silicide layers.

Semiconductor structures and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a doped region in a substrate and comprising a first-type dopant, a plurality of nanostructures disposed directly over the doped region, a gate structure wrapping around each nanostructure of the plurality of nanostructures, a first epitaxial feature and a second epitaxial feature coupled to the plurality of nanostructures, wherein each of the first epitaxial feature and the second epitaxial feature comprises the first-type dopant, a first insulation feature disposed between the first epitaxial feature and the doped region, and a second insulation feature disposed between the second epitaxial feature and the doped region.

The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure includes forming a stack of channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shape structure, forming a dummy gate stack over a channel region of the fin-shape structure, recessing a source/drain region to form a source/drain trench, forming an epitaxial feature in the source/drain trench, after the forming of the epitaxial feature removing the dummy gate stack, releasing the channel layers in the channel region as channel members, forming a gate structure wrapping around each of the channel members, and after the forming of the gate structure performing an ion implantation to increase a dopant concentration of a dopant in the epitaxial feature.