A transistor structure with a multi-layer field plate and related methods are disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a field plate on the thicker portion of the dielectric layer.

A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

An integrated circuit structure includes a semiconductor substrate, a first source/drain feature, a second source/drain feature, a gate dielectric layer, a gate electrode, a field plate electrode, and a dielectric layer. The semiconductor substrate has a well region and a drift region therein. The first source/drain feature is in the well region. The second source/drain feature is in the semiconductor substrate. The drift region is between the well region and the second source/drain feature. The gate dielectric layer is over the well region and the drift region. The gate electrode is over the gate dielectric layer and vertically overlapping the well region. The field plate electrode is over the gate dielectric layer and vertically overlapping the drift region. The dielectric layer is between the gate electrode and the field plate electrode. A top surface of the gate electrode is free of the dielectric layer.

A semiconductor device with ESD protection structure and a method of making it are disclosed. The semiconductor device with ESD protection structure includes at least one gate and source and drain regions on opposite sides of the at least one gate that constitute at least a discharging MOSFET. The gate includes first gate portions having a first dopant concentration and a second gate portion having a second dopant concentration. The first dopant concentration is lower than the second dopant concentration. The at least one first gate portions are lower portions of the gate above the edges of an active area, and the second gate portion is the remaining portion of the at least one gate other than the first gate portions.

A structure of a semiconductor device, including a substrate, is provided. A first gate insulating layer is disposed on the substrate. A second gate insulating layer is disposed on the substrate. The second gate insulating layer is thicker than the first gate insulating layer and abuts the first gate insulating layer. A gate layer has a first part gate on the first gate insulating layer and a second part gate on the second gate insulating layer. A dielectric layer has a top dielectric layer and a bottom dielectric layer. The top dielectric layer is in contact with the gate layer, and the bottom dielectric layer is in contact with the substrate. A field plate layer is disposed on the dielectric layer and includes a depleted region, and is at least disposed on the bottom dielectric layer. A method for fabricating the semiconductor device is provided too.

Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.