A junction field effect transistor (JFET) includes a drift region disposed on a substrate that includes a drain region of the JFET. A lower gate region is disposed on the drift region, a source region is disposed above the lower gate region, and an upper gate region at least partially surrounding the source region and extending laterally beyond the lower gate region is disposed above the source region. The upper gate region extends laterally beyond the lower gate region by a distance defining a gate offset width between the upper gate region and the lower gate region.

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

A performance of a power semiconductor device is improved. A power semiconductor device including unit cells UR and UL cyclically arranged in an X direction and a Y direction perpendicular to each other and a plurality of end cells is used. The unit cells UR and UL are alternately arranged in the X direction, the plurality of end cells include an X-end cell XL, Y-end cells YR and YL, an XY-end cell XY1L, and an XY-end cell XY2L for an optional region, each number of arrangement cycles of the unit cells UR and UL in the Y direction changes depending on repetition cycle coordinates in the X direction, each of the cyclically-arranged unit cells UR and UL is adjacent to any of the plurality of end cells at an endmost portion of arrangement cycle in each of the X direction and the Y direction, and regions having the plurality of end cells are different in an electric property from the unit cells UR and UL.

Disclosed are a structure, including a junction field effect transistor (JFET), and a method of forming the structure. The JFET includes a channel region and source and drain regions above the channel region. The JFET also includes a first gate region below the channel region and a second gate region above the channel region positioned laterally between and isolated from the source and drain regions. The first gate region underlies the drain region and is offset from the source region and at least that portion of the second gate region adjacent to the source region. Specifically, the first gate region is either completely offset from both the source region and the second gate region or is completely offset from the source region and only partially underlies the second gate region. In the JFET, resistance on is reduced and saturation drain current is increased without significantly impacting breakdown or pinch-off voltages.

A nitride semiconductor transistor device is disclosed to provide a normally-off nitride semiconductor transistor device which is excellent in switching properties with less dispersion of the properties. The nitride semiconductor transistor device has a buffer layer, a GaN layer, and an AlGaN layer in turn grown on a substrate. A first insulating film, a charge storage layer, a second insulating film, and a control electrode are in turn grown on the AlGaN layer. A source electrode and a drain electrode are formed to sandwich the charge storage layer over the AlGaN layer. A threshold voltage to shut off an electric current flowing between the source and drain electrodes through a conductive channel induced at an interface of the AlGaN layer and the GaN layer is made positive by adjusting charge stored in the charge storage layer.

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.