H10D30/6215

Display device using semiconductor light-emitting element, and manufacturing method therefor
12170345 · 2024-12-17 · ·

The present invention provides a display device using a semiconductor light-emitting element and a manufacturing method therefor, the display device transferring semiconductor light-emitting elements on a temporary substrate, and then directly implementing, through a stack process, the structure of a wiring substrate on the temporary substrate on which the semiconductor light-emitting elements are arrayed, thereby enabling the semiconductor light-emitting elements and the wiring substrate to be electrically connected.

ROLL TO ROLL SINTERING SYSTEM FOR WIDE INORGANIC TAPE MATERIAL AND SINTERED ARTICLES

A roll-to-roll sintering system for wide inorganic tape material may include a spool on which is wound a continuous tape material comprising a green tape material and a backing layer, a take-up reel, and a heating station including at least one furnace. The heating station is configured to receive an unwound length of the continuous tape. The heating station further includes a first curved section such that the continuous tape material is bent through a radius of curvature of 0.01 m to 13,000 m, and at least two rollers defining the first curved section over which the continuous tape material is bent. The heating station is controlled to provide at least a portion of the heating station with an air free atmosphere, that being at least one of vacuum, hydrogen, or helium.

SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND DISPLAY DEVICE
20240413269 · 2024-12-12 · ·

This semiconductor light emitting device includes an emission layer, a passivation layer on the emission layer, and a first adhesive layer on the passivation layer. The passivation layer may include a plurality of grooves, and the first adhesive layer may be disposed in each of the plurality of grooves. Arranging the first adhesive layer in the plurality of grooves may enhance fixability. The display device includes a plurality of semiconductor light emitting devices. The semiconductor light emitting devices may include a horizontal semiconductor light emitting device, a flip chip semiconductor light emitting device, or a vertical semiconductor light emitting device.

WAVELENGTH CONVERTER AND WAVELENGTH CONVERSION MATERIAL USING THE SAME

A wavelength converter including, as semiconductor nanoparticles, a first semiconductor nanoparticle that converts light with a wavelength of 450 nm into light with a wavelength .sub.1 nm, and a second semiconductor nanoparticle that converts light with a wavelength of 450 nm into light with a wavelength .sub.2 nm, in which the wavelength .sub.1 and the wavelength .sub.2 satisfy .sub.1>.sub.2>450, and a relation between an emission intensity I.sub.1b and an emission intensity I1a satisfies I.sub.1a<I.sub.1b, where I.sub.1b is an emission intensity at the wavelength .sub.1 when the wavelength converter including the first and second semiconductor nanoparticles is irradiated with light with a wavelength of 450 nm and an excitation photon number N.sub.0, and I.sub.1a is an emission intensity at the wavelength .sub.1 when a wavelength converter including only the first semiconductor nanoparticle is irradiated with the light with a wavelength of 450 nm and an excitation photon number N.sub.0.

METHOD FOR MANUFACTURING LIGHT EMITTING DIODE STRUCTURE

A method for manufacturing an LED structure includes forming a first semiconductor layer on a first substrate; performing a first implantation operation to form a first implanted region and a first non-implanted region in a second doping semiconductor layer of the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; performing a second implantation operation to form a second implanted region and a second non-implanted region in a fourth doping semiconductor layer of the second semiconductor layer; performing a first etch operation to remove a portion of the second semiconductor layer and expose at least the first non-implanted region; performing a second etch operation to expose a plurality of contacts of a driving circuit formed in the first substrate; and electrically connecting the first non-implanted region and the second non-implanted region with the plurality of contacts.

Ferroelectric channel field effect transistor

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

TRIPLE-GATE MOS TRANSISTOR AND METHOD FOR MANUFACTURING SUCH A TRANSISTOR

A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor.

Semiconductor device structure with metal gate stacks

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a first conductive material and a second conductive material disposed over the semiconductor substrate and the first dielectric layer. The semiconductor device structure further includes a second dielectric layer surrounding the first conductive material and the second conductive material and an insulating structure over the semiconductor substrate. The insulating structure is disposed between the first conductive material and the second conductive material. The insulating structure comprises a material different from the first dielectric layer and the second dielectric layer.

Self light emitting apparatus, liquid crystal display apparatus, and manufacturing method for self light emitting apparatus

The present disclosure has an object to hinder reduction of a yield due to a failure in an LED element or a mounting failure in a self light emitting apparatus. In a self light emitting apparatus, each pixel includes one basic cell and at least one redundant cell as a subpixel. The redundant cell includes an LED element that emits light of a color the same as at least one LED element out of LED elements included in the basic cell. A plurality of subpixels included in each pixel are configured as a subpixel group being an assembly that includes a plurality of LED elements being integrated. An array pitch of the subpixels in the subpixel group is smaller than an array pitch of the subpixels in adjacent ones of a plurality of subpixel groups.