In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is off (Vg approximately 0 volts). When the transistor is on (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is off (Vg approximately 0 volts). When the transistor is on (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

Systems, methods, and apparatus for an improved body tie construction that produces all the benefits of conventional body tie (H-gate, T-gate), without the limitations and degradations associated with those constructions are described. The improved body tie construction is configured to have a lower resistance body tie when the transistor is off (Vg approximately 0 volts). When the transistor is on (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie.

A method of forming a substrate contact in a vertical transistor device includes patterning a sacrificial layer to form an opening in the sacrificial layer, the sacrificial layer disposed on hardmask arranged on a substrate, and the substrate including a bulk semiconductor layer, a buried oxide layer arranged on the bulk semiconductor layer, and a semiconductor layer arranged on the buried oxide layer; forming oxide spacers on sidewalls of the opening in the sacrificial layer; using the oxide spacers as a pattern to etch a trench through the substrate, the trench stopping at a region within the bulk semiconductor layer; and depositing a conductive material in the trench to form the substrate contact.

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device.

Devices and methods for forming a device are disclosed. The method includes providing a crystalline-on-insulator substrate having a bulk substrate and a surface substrate separated by a buried insulator layer. The surface substrate is defined with a device region. A transistor having a gate is formed in the device region. A first diffusion region is formed adjacent to a first side of the gate and a second diffusion region is formed adjacent to and displaced away from a second side of the gate. At least a first drift isolation region is formed in the surface substrate adjacent to and underlaps the second side of the gate. A drift well is formed in the surface substrate encompassing the first drift isolation region. A device isolation region surrounding the device region is formed in the surface substrate. The device isolation region includes a second depth which is deeper than a first depth of the first drift isolation region.

New, distinct, and useful architectures for single-legged SOI-MOS were established and fabricated for the very first time. They incorporated into their architectures an innovative new configuration to wire the device Body to the Body-Tied-Source. This new configuration drastically increased the conductance between the Body and the Body-Tied-Source. This consequently allowed these devices to effectively support much higher operating biases. Same configuration also functioned on structures with very large peripheries. These gave proportional increase in this same conductivity, and for same area-efficiency, with the increase of their peripheries to accommodate higher currents. The functional model that governs this proportional scaling in these new architectures for single-legged SOI-MOS devices was established and is being claimed through this patent for the very first time. Through it, single-legged SOI-MOS devices will efficiently scale to area-efficient ultra large peripheries with minimal hits to their bandwidth.