Approach for an area-efficient and scalable CMOS performance based on advanced Silicon-On-Insulator (SOI), Silicon-On-Sapphire (SOS) and Silicon-On-Nothing (SON) technologies

Abstract

New, distinct, and useful architectures for single-legged SOI-MOS were established and fabricated for the very first time. They incorporated into their architectures an innovative new configuration to wire the device Body to the Body-Tied-Source. This new configuration drastically increased the conductance between the Body and the Body-Tied-Source. This consequently allowed these devices to effectively support much higher operating biases. Same configuration also functioned on structures with very large peripheries. These gave proportional increase in this same conductivity, and for same area-efficiency, with the increase of their peripheries to accommodate higher currents. The functional model that governs this proportional scaling in these new architectures for single-legged SOI-MOS devices was established and is being claimed through this patent for the very first time. Through it, single-legged SOI-MOS devices will efficiently scale to area-efficient ultra large peripheries with minimal hits to their bandwidth.

Claims

1. A single-leg Silicon-On-Insulator Metal-Oxide-Semiconductor (SOI-MOS) comprising; a highly P-doped pocket (P_pocket) that interfaces on one side the full peripheral width of the MOS structure while it junctions the source on the opposite side, the P_doped pocket has a higher doping relative to a P_Body, this higher doping can be one to many orders of magnitude higher, this arrangement imposes a hard barrier for an impact-Ionizations current in the P_body to laterally diffuse through this junction and forces it to conduct through the P_pocket along the wider peripheral width of the structure to new and distinct configurations of a body tied source (BTS) that connects to the P_pocket, these new configurations specifically split the impact ionization current (II-current) into parallel paths, increasing therefore the overall equivalent conductance between the P_Body and BTS; the lateral dimensions of the P_pocket are made to be relatively wide so to significantly increase its conductance, the P_pocket width (Wp) extends laterally no more than of P-body width (LGeff), the BTS has corner-rounded dimensions that suppress current-crowding of the II-current and further increases the overall conductance between the P_Body and the BTS; higher Impact-Ionization (II-current) resulting from wider full peripheral width of this single-leg MOS device structure requires proportional scale-up of the equivalent conductance between the P_Body and BTS; this is accomplished through insertion of additional BTS stripes; the device layout area is most area-efficient, that is it possesses highest drive current for given WGeff, Bipolar leakage, and operating bias, when the number of its BTS stripes (N) and the spacing(s) between them conform to the model, $\mathrm{II}-\mathrm{current}=I_{\mathrm{Bipolar}}+\mathrm{Vdrop}+N\left(q{}_h\mathrm{conc\_}\right)\frac{\mathrm{Wp}\left(\mathrm{tsi}-\mathrm{Depl}\max \right)4}{\mathrm{SPAC}}$
WGeff=NSPAC; N1 is the number of BTS stripes from given value for suppressed Bipolar leakage (I.sub.Bipolar) a corresponding magnitude for Vdrop is determined; the number of required stripes for BTS (N), and the required spacing(s) between them (SPAC) are then extracted for given II-current from the above model, the claim extends to devices fabricated on any buried dielectric beside the Silicon-dioxide, this includes Silicon-On-Sapphire (SOS), Silicon-On-Nothing (SON), and all the insulating substrates (e.g. flexible organic substrates).

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) FIG. 1: Comparative drawn schematics illustrating the comparison between one non-optimal layout of an SOI-NMOS (left-hand side) versus an optimized layout design (right-hand side) of a same device. The non-optimal design used extra unneeded BTS area to meet targeted electric specifications with a fully suppressed FBE; the optimized design used on the other hand minimum possible BTS area for an equal suppression of FBE at same electric specifications and same total peripheral layout area. The WGeff in the optimized design is higher and so are its drive current and speed.

(2) FIG. 2A: Top view schematic of a proprietary single-legged SOI-NMOS device architecture that is being claimed in this patent. It ensures highest possible conductance between P_Body and BTS for given device periphery layout. This highest conductance is realized through the implantation of very highly conductive channel or canal (P_Pocket) that interfaces on its one side the full peripheral width of the structure while it junctions the Source on its opposite side. This higher doping of this pocket (P_Pocket) relative to P_Body (generally one- to two-orders higher) imposes hard barrier for II-current in P_Body to laterally diffuse through this junction and forces it to split instead into paralleled paths and conduct to the narrow BTS stripe through this P_Pocket along the much wider WG. These paralleled paths for II-current double the equivalent conductance between P_Body and BTS for given WG. A narrow WB is essential for area-efficiency as the Silicon volume from BTS does not contribute to device current. Smooth corner-rounding of the BTS edges suppresses current-crowding and boost the equivalent conductance. Gate, its dielectric, and Spacers regions are not shown. Gate and its dielectric are shown in the side views of FIG. 3 A, FIG. 3 B and FIG. 3 C that further describe this same singled-leg SOI MOS device structure. The LG symbolizes the Gate-Length.

(3) FIG. 2B: Schematic illustrating the conductive path for Impact-Ionization current in the device structure of FIG. 2 A. The II-current in P_Body sees the equivalence of two-times the conductance of the highly doped P_Pocket due to this optimum positioning of the BTS along the WG.

(4) FIG. 3 A: Cartoon schematic showing the corresponding Front view of the same claimed proprietary architecture of FIG. 2 A based on either the SOI or the SOS. The spacers on both lateral ends of the Gate are not being shown; they can be same as in any standard CMOS process. The view is perpendicular to the conducting inversion channel. (Back view is similar).

(5) FIG. 3 B: Cartoon schematic showing the Side view from the Source side of the same claimed architecture of FIG. 2 A based on either the SOI or the SOS.

(6) FIG. 3 C: Cartoon schematic showing the side view from the Drain side of the same claimed proprietary architecture of FIG. 2 A based on either the SOI or the SOS.

(7) FIG. 4: Cartoon schematic showing the corresponding front view of the claimed proprietary architecture of FIG. 2 A, but based on SON, (the back view is similar). Its side views are similar to those of FIG. 3 B and FIG. 3 C, but without the BOX/SOS layer and with N+ Source and N+ Drain extending vertically to the Back-Gate Silicon film. Similarly, Spacers on both lateral ends of the Gate are not shown; they can be same as in any standard CMOS process.

(8) FIG. 5: An illustrative top-view layout of an optimized higher-current single-legged SOI-NMOS device that uses 4 BTS stripes for optimization. Its effective Gate width is: (4+1)SPAC.Gate, its dielectric, and Spacers regions are not shown.

(9) FIG. 6 A: Top view schematic of another proprietary single-legged SOI-NMOS device that is also being claimed in this patent. It similarly splits the Impact-Ionizations current through Pocket into two paralleled paths that ensure similar highest conductance between Body and BTS for given WG. Its minor drawback compared to the layout of FIG. 2 A is that it requires one additional BTS stripe for a same WGeff. Its advantage is that it does conduct device current toward the center of its WG where the defects density tends to be naturally lower. Gate, its dielectric, and Spacers regions are not shown. Gate and its dielectric are shown in the side views of FIG. 7 A and FIG. 7 B. Its side view on the Drain side is same as that of FIG. 3 C.

(10) FIG. 6 B: Schematic illustrating the conductive path for Impact-Ionization current in the device structure of FIG. 6 A. The II-current in P_Body sees the equivalence of two times the conductance of the highly doped P_Pocket due to another optimum positioning of the BTS along the WG.

(11) FIG. 7 A: Cartoon schematic showing the corresponding Front view of the same claimed proprietary architecture of FIG. 6 A based on either the SOI or the SOS. The spacers on both lateral ends of the Gate are not being shown; they can be same as in any standard CMOS process. The view is perpendicular to the conducting inversion channel. (Back view is similar).

(12) FIG. 7 B: Cartoon schematic showing the Side view from the Source side of the same claimed architecture of FIG. 6 A based on either the SOI or the SOS.

(13) FIG. 8: Cartoon schematic showing the corresponding front view of the claimed proprietary architecture of FIG. 6 A, but based on SON, (the back view is similar). Its side views are similar to those of FIG. 7 B and FIG. 3 C, but without the BOX/SOS layer and with BTS and N+ Drain extending vertically to the Back-Gate Silicon film. Similarly, Spacers on both lateral ends of the Gate are not shown; they can be same as in any standard CMOS process.

(14) FIG. 9: A 3D TCAD simulation illustrating the impact of extra summative BTS areas on the WGeff in a large-periphery 1-leg FD-SOI NMOS. As more BTS area gets consumed within the total layout periphery of the device, the conductive path for electron current gets reduced, and therefore the effective Gate-Width (WGeff) of the device is also reduced. A total of eleven BTS stripes were utilized in that simulation.

(15) Key concept in our guided design approach is that it maintains for the targeted (desired) electric specifications such summative total area consumed by BTS to a very minimum while effectively suppressing the FBE.

(16) FIG. 10: A 3D TCAD simulation illustrating the parasitic Bipolar latch-up in an un-optimized large-periphery 1-leg FD-SOI NMOS based on the device structure of FIG. 6 A. Shown is LOG.sub.10 of the Recombination Rate. As shown, Diffusion current is strongest toward the center between 2 BTS where the voltage-drop in P_Pocket due to the conducting Holes from Impact-ionization is highest, and so is the barrier lowering.

(17) FIG. 11: Simulation of the Body potential in a fully optimized large-periphery 1-leg FD-SOI NMOS. It exhibited less than a 0.1V throughout its P_Body. The device was optimized in the back-accumulation mode (with an applied negative bias to its Back-Gate, in addition to the positive bias for inversion at the Front-Gate). WB=0.5 m.

(18) FIG. 12: Measured and simulated Current-Voltage transfer curves of FD-SOI NMOS devices (WGeff=9.5 m; LG=0.35 m; VD=3.6V); Box=0.5 m; CFox10 nm; tsi=35 nm; WB=m). Clearly shown is the Bipolar effect in a device that failed to maintain a voltage drop throughout its P_Pocket that maintained effective suppression of the Bipolar current. The optimal device that effectively suppressed the Bipolar effect corresponds to that of the TCAD simulation in FIG. 11.

(19) FIG. 13: Measured and simulated Subthreshold-Slope (SS), from 3D TCAD, in our optimized FD SOI NMOS (WGeff=2 m; LG=0.35 m; VDS=3.6V; Box=0.5 m; tox10 nm; tsi=35 nm). Its relatively high SS of 98 mV/Dec is caused from the effect of its highly doped P_Pocket. (Typical values for SS are: 65-80 mV/Dec with FD SOI; 80-120 mV/Dec with PD SOI; and 120 mV/Dec with bulk Si substrate).

DETAILED DESCRIPTION OF THE INVENTION

(20) A top-view of such device layout is depicted in FIG. 2 A. Further schematics describing its structures are shown in FIG. 3 A, FIG. 3 B, and FIG. 3 C. The P Pocket extends into the effective Gate-Length of the device (LGeff) a distance: Wp that by default can be no more than LGeff. This ensures the P_Pocket to be conductive with no stiff penalty on the device VT. A tighter or a more loose constraint may always be set for the specific application. As is shown with the dashed-arrows in FIG. 2 A, the device structure splits the II-current that generates around its Drain's edge into two equal magnitudes that converge through separate paths to the BTS while conducting in P_Pocket. The dashed-rectangle in same figure shows region within the device structure that does not conduct device current, and no consequent Impact-Ionizations occur within it either in following the II-current model described by X. Gu et al.;

(21) $\mathrm{II}-\mathrm{current}=I_{\mathrm{device}}\left[\frac{}{}\left(\mathrm{VD}-\mathrm{Vknee}\right){}^{-\frac{\mathrm{lm}}{\mathrm{VD}-\mathrm{Vknee}}}\right].$
, , lm and are parametrization constants. A lateral device current needs to conduct through this region to kick Impact-Ionizations, and which it does not. This also reduces the portion from WG that conducts device current to WGeff=(N+1)SPAC=2SPAC (N is the number of narrow stripes used for BTS. N=1 in FIG. 2 A), with

(22) $\mathrm{SPAC}\frac{\mathrm{WG}-\mathrm{WB}}{2}.$
WB is the width of the very narrow BTS stripe(s) that interface(s) the P_Body along the WG. As is intuitive from the above equation, the II-current does increase with WGeff since the I.sub.device increases with WGeff. Part of the II-current conducts through this P_Pocket while its other part leaks through the lateral junction between Body and Source. The corresponding equation for the currents-balance from Kirchoff-Current-Law (KCL) is:

(23) $\frac{\mathrm{II}-\mathrm{current}}{N+1}=\frac{I_{\mathrm{Bipolar}}\left(\mathrm{Vdrop}\right)}{N+1}+\mathrm{Vdrop}\mathrm{P\_Pocket}.$
Vdrop is the voltage-drop in P_Pocket from the portion of II-current that conducts through it. .sub.P.sub._.sub.Pocket is the conductance of P_Pocket on each side of the BTS. Its analytic model from simple device Physics is:

(24) $\begin{array}{cc}\mathrm{P\_Pocket}=\frac{1}{}\frac{\mathrm{area}}{\mathrm{length}}=\left(q{}_h\mathrm{NA}\right)\frac{\mathrm{Wp}\left(\mathrm{tsi}-\mathrm{Deplmax}\right)}{\mathrm{SPAC}}& \left(1\right)\end{array}$
q is the electron-charge unit, .sub.h the Hole-Mobility in P_Pocket, and NA the doping concentration in this P_Pocket.

(25) The above expression for .sub.P.sub._.sub.Pocket does not account to the effect of lateral depletion in P_Pocket since a lightly doped region at Source (N) absorbs most of this junction depletion. The expression still accounts nonetheless to the impact of the transversal depletion in P_Pocket while considering the worst-case scenario through which that P_Pocket strongly inverts. Expression for this transversal depletion is:

(26) $\mathrm{Deplmax}=2\sqrt{\frac{\mathrm{.Math.}\mathrm{tsi}p}{q\mathrm{NA}}},$
with

(27) $p=\mathrm{vth}\ln \left(\frac{\mathrm{NA}}{\mathrm{ni}}\right).$
tsi is the electric-dielectric constant of Silicon, and ni is the intrinsic carrier concentration of Silicon.

(28) The expression for the KCL balance for currents can be rewritten as:
II-current=I.sub.Bipolar(Vdrop)+Vdrop(N+1).sub.P.sub._.sub.Pocket(2)

(29) In substituting equation (1) into equation (2) it is obtained:

(30) $\begin{array}{cc}\mathrm{II}-\mathrm{current}=I_{\mathrm{Bipolar}}\left(\mathrm{Vdrop}\right)+\mathrm{Vdrop}\left(N+1\right)\left(q{}_h\mathrm{NA}\right)\frac{\mathrm{Wp}\left(\mathrm{tsi}-\mathrm{Deplmax}\right)}{\mathrm{SPAC}}& \left(3\right)\end{array}$

(31) Equation (2) states that an equivalent conductance seen from the P_Body of the device of FIG. 2 A is: (N+1).sub.P.sub._.sub.Pocket=2.sub.P.sub.Pocket. This compares to a conductance of:

(32) $\frac{\mathrm{P\_Pocket}}{2}$
if the BTS stripe was connected instead at the very edge of the WG in FIG. 2 A and with an exact same WGeff=(N+1)SPAC=2SPAC. That is an increase by factor of 4, simply from optimum positioning of the same BTS stripe along the WG for a same WGeff. Due to the finite magnitude of .sub.P.sub._.sub.Pocket at any given magnitudes for Wp, NA, .sub.h, and tsi, the structure of FIG. 2 A (with N=1) cannot Manage the high magnitudes of II-current from devices with very large peripheries while it still suppresses the parasitic Bipolar current.

(33) Significant Bipolar leakage will occur then. The fix is to array the device structure of FIG. 2 A along its Z-axis with added BTS stripes in-between structures. This will further split the II-current among mote paralleled structures of same .sub.P.sub._.sub.Pocket. The equivalent conductance seen from P_Body for the arrayed structure will still scale in proportion to: (N+1).sub.P.sub._.sub.Pocket. A schematic for such an arrayed structure is shown in FIG. 5. With N=4, and WGeff=5SPAC. Equivalent conductance seen from P_Body scales to 5.sub.P.sub._.sub.Pocket.

(34) Key criterion is to design for largest possible SPAC at fixed magnitudes of WGeff, WB, tsi, Wp, and a tolerated magnitude for the Bipolar leakage due to II-Current from the given bias (a rule-of-thumb is to design this Bipolar leakage an order-of-magnitude lower than the I.sub.Device). This large SPAC, along with the narrow WB stripe(s), is what ensures, at the given bias, the best area-efficiency for layout (such that WGeff is closest to WG), and the adequate suppression of the device built-in parasitic Bipolar structure.

(35) The general procedure for the design is: 1The required WGeff for the device to deliver its operating current target (its desired current) at its short-channel VT can be extracted in following the DC models for currents as described by Kwyro Lee, Michael Shur, Tor A. Fjeldly, and Trond Ytterdal, Semiconductor Device Modeling for VLSI, New Jersey: Prentice Hall, pp. 238-256, 1993. 2Value for the I.sub.Bipolar (Vdrop) is affixed to a magnitude significantly lower than the I.sub.Device (e.g. one-order of magnitude lower), and one accurate model for the Bipolar current is used to extract the corresponding Vdrop magnitude to this affixed magnitude for the I.sub.Bipolar (Vdrop). One recommended model can be that described by Ben G. Streetman, Solid State Electronic Devices, 4.sup.th ed. New Jersey: Prentice Hall, pp. 244-247, 1995. 3From the targeted (or desired) values for VD and I.sub.Device the II-current is then extracted for the specific WGeff from the Impact-Ionizations model described by X. Gu et al.

(36) Note that for the accurate extractions of all of the WGeff, Vdrop, and II-current at the targeted (or desired) VD and I.sub.Device, the utmost accurate parametrization constants reflecting on the specific fabrication-process must be utilized in the models for DC MOS currents, for Bipolar leakage, and for Impact-Ionizations.

(37) Specifically-built test-structures on test-chips (or test-vehicles) are utilized for the accurate extractions of these parametrization constants for their models prior to utilizing the models. Same test-structures are also used to extract the .sub.h. It is highly critical to de-convolute the impact from Bipolar current on the II-current in the extractions of all the parametrization constants. For that purpose, all the extractions are done on test-structures of different peripheries and that are ultra-dense in their BTS stripes (they axe very area-inefficient, but their purpose is for no other than extracting precise values for models constants). This allows to accurately gauge magnitudes for II-current and the I.sub.device at the high biasing, independent of effect of the Bipolar.

(38) The number of required stripes for BTS (N) and the required spacing(s) between stripes (SPAC) are then extracted iteratively from the system-model below:

(39) $\mathrm{II}-\mathrm{current}=I_{\mathrm{Bipolar}}+\mathrm{Vdrop}\left(N+1\right)\left(q{}_h\mathrm{NA}\right)\frac{\mathrm{Wp}\left(\mathrm{tsi}-\mathrm{Deplmax}\right)}{\mathrm{SPAC}}$
WGeff=(N+1)SPAC N is then rounded to its higher integer value. Ratio: SPAC is adjusted to mirror the rounding of N.

(40) Daghighi et al. recognized through his work on PD-SOI MOS: Arash Daghighi, Mohamed Osman, and Mohamed A. Imam, An area efficient body contact for low and high voltage SOI MOSFET devices, Solid-State Electronics, vol. 52, iss. 2, pp. 196-204, February 2008, that the insertion of many more BTS stripes reduces the Body potential caused from Impact-ionizations and can alleviate the FBE and the Bipolar latch-up, which in may allow a degree of scale-up for larger WGeffs and currents. He failed to realize though that the added incorporation of very highly conductive channel/canal in the device Body, along its entire width, and that junctions the Source and ties all the BTS stripes together can dramatically reduce this Body potential to permit significant reduction of the BTS stripes required to maintain adequate suppression of the Bipolar effects. This would have consequently resulted in larger WGeff and higher current for same total peripheral area of layout (footprint). Such highly conductive channel/canal can be generally doped with two orders of magnitude higher than Body and will extend into it a distance no less than quarter, that of the Gate-length. This is what would have given the device its much superior conductivity toward the BTS stripes. Daghighi et al. did not realize either that his same device layout is not effective for the FD-SOI MOS as the high II-current will opt to shorten to the Source through the an already-lowered lateral barrier rather than to conduct to BTS through the very high resistivity of the fully-depleted Body.

(41) Design that can be closest to the new innovative device structures that are introduced through this patent is that of U.S. Pat. No. 5,185,280 (Theodore W. Houston et al., US005185280A, FIG. 4 & FIG. 4a). This design accounts to the advantage of tying the BTS implant to Halo pocket, but fails to realize that for given WGeff there exists optimal configuration for BTS that best increases the equivalent conductance between P_Body and BTS. Consequently, the equivalent conductivity between the Body and the BTS in that design is significantly lower to what is obtained through the patented device structures in this application (by more than a factor of 4). Furthermore, the design in that patent does not entirely separate the whole Body region from the lightly doped Source region. Consequently, the conducting area of Halo to BTS is low, and so is the total equivalent conductance between P_Body and BTS. Additionally, the Holes from Impact-Ionizations tend to fail confining within. Halo and opt instead to follow a less resistive path through forward-biasing the weaker lateral junction between the LDD at Source and the Body.

(42) Another proprietary device structure for singled-legged SOI-NMOS is shown in FIG. 6A, FIG. 7 A, and FIG. 7 B. It results in same equivalent high conductance between P_Body and BTS as that of FIG. 2 A, bits with different style connectivity of P_Pocket to BTS.

(43) Table 1 displays device parameters for the optimization performed on the device structure of FIG. 11 and FIG. 12 following the general design procedure described in this section. Table 2 shows the parameterization constants that were extracted from the specifically-built test-structures, and the design equations used from the models

(44) Additional models were used to account to the long-channel and the short-channel VTs. Model for the long-channel VT was taken from the work of Hyung-Kyu, student member, IEEE, and Jerry G. Fossum, Fellow, IEEE, Threshold voltage of thin-film Silicon-On-Insulator (SOI) MOSFET's, IEEE Trans. Electron Devices, vol. 30, no. 10, pp. 1244-1251, October 1983. And, model to correct this VT for short-channel effects independently from the impact of II-current was taken from the work of Bin Yu et al., Short-channel effect improved by lateral channel Engineering in deep-submicrometer mosfet's, IEEE Trans. Elec. Dev., vol. 44, no. 4, pp. 627-634, April 1997.

(45) TABLE-US-00001 TABLE 1 Process Parameters and the design optimization on FD-SOI MOSFET Value Processparameter Tsi, (nm) 35 Tox, (nm) 9 BOX, (nm) 500 LGeff, (nm) 350 Target Bias VGS 0.8 Optimization Wp (nm) 24 NB(cm.sup.3) 4 10.sup.17 NA (cm.sup.3) 8 10.sup.19 N- (cm.sup.3) 5 10.sup.19 WGeff (m) 9.5 VGB (V) 0.8

(46) TABLE-US-00002 TABLE 2 Design Equations and the equation-based design flow for optimization Design Example // Sec. I - CONSTANTS: Electric dielectric constant in space. o = 8.85 x 10.sup.12 (F/m) Relative dielectric constant of Silicon. si = 11.68 relative dielectric constant of Silicon Dioxide. ox = 3.9 Default (or extracted) value for electron channel mobility. n = 1350 10.sup.4 (m.sup.2/(V .Math. s)) Default (or extracted) value for Hole mobility. h = 480 10.sup.4 (m.sup.2/(V .Math. s)) Default value for electron Saturation-Velocity. vsat = 1e5; vsat = 10.sup.5 (m/s) Default values for parameters defining impact-ionization current. 0$\frac{}{}=4{10}^5\left(1/V\right)$ lm = 50 = 0.5 Workfunction at the front Gate (Default or extracted). .sub.MS.sup.f = 0.75 (V) Workfunction at the back gate (default or extracted). .sub.MS.sup.b = 0.5 (V) Intrinsic carrier concentration of Silicon. ni = 1.5 10.sup.16 (m.sup.3) Thermal-Voltage at room temperature. vth = 26 10.sup.3 (V) Parasitic fixed charge density at the semiconductor and front Oxide interface. Qff = 5 10.sup.9 (1/m.sup.2) Parasitic fixed charge density at the semiconductor and BOX. Qfb = 5 10.sup.14 (1/m.sup.2) Electron charge unit. q = 1.6 10.sup.19 (C) Correction factor accounting to charging in BOX. Corr = 0.8 // Sec. II - Technology-node specific process parameters and dimensions: Physical thickness of front Silicon film. tsi = 35 10.sup.9 (m) Physical thickness of BOX. BOX = 0.5 10.sup.6 (m) Physical thickness of front oxide. tox = 9 10.sup.9 (m) Effective Gate length or channel length. LGeff = 0.35 10.sup.6 (m) Effective Gate width. WGeff = 2 10.sup.6 (m) Constant capturing DIBL effect between technology nodes. = 1.5 // Sec. III - Design Equations for Calculation of threshold-voltage independent of short-channel effects. Case-1: The Back-Surface of Front-Silicon film that interfaces the BOX is depleted: $\mathrm{VTHO}={}_{\mathrm{MS}}^f-\frac{q\mathrm{Qff}}{\mathrm{CFox}}+2B-\frac{q\mathrm{Nb}\mathrm{tsi}}{2\mathrm{CFox}}+\frac{\mathrm{.Math.o}\mathrm{.Math.si}}{t\mathrm{si}\mathrm{CFox}}\left(2B-\mathrm{sb}\right)$ Eq. 1 $B=\mathrm{vth}\ln \left(\frac{\mathrm{Nb}}{\mathrm{ni}}\right)$ $\mathrm{CFox}=\frac{\mathrm{.Math.}o\mathrm{.Math.ox}}{\mathrm{tox}}$ Eq. 2 ${}_{\mathrm{sb}}=\frac{\mathrm{CBOX}}{\mathrm{CBOX}+\mathrm{Cb}}\left(V_{\mathrm{GB}}-V_{\mathrm{GB},\mathrm{acc}}\right)$ Eq. 3 $\mathrm{Cb}=\frac{\mathrm{.Math.}o\mathrm{.Math.si}}{\mathrm{tsi}}$ Eq. 4 $\mathrm{CBOX}=\frac{\mathrm{.Math.o}\mathrm{.Math.ox}}{\mathrm{Corr}\mathrm{BOX}}$ Eq. 5 $V_{\mathrm{GB},\mathrm{acc}}={}_{\mathrm{MS}}^b-\frac{\mathrm{Qfb}}{\mathrm{CBOX}}-\frac{\mathrm{Cb}}{\mathrm{CBOX}}2B-\frac{q\mathrm{Nb}\mathrm{tsi}}{2\mathrm{CBOX}}$ Eq. 6 Case-2: The Back-Surface of Front-Silicon film that interfaces the BOX is inverted: In that case the VGB in Eq. 3 is large enough to bring the sb equaling 2 B, and the VTHO of Eq. 1 converges to: $\mathrm{VTHO}={}_{\mathrm{MS}}^f-\frac{q\mathrm{Qff}}{\mathrm{CFox}}+2B-\frac{q\mathrm{Nb}\mathrm{tsi}}{2\mathrm{CFox}}$ Eq. 7 Case-3: The Back-Surface of Front-Silicon film that interfaces the BOX is accumulated: At the onset of accumulation the sb of Eq. 1 equals 0, and the VTHO converges to: $\mathrm{VTHO}={}_{\mathrm{MS}}^f-\frac{q\mathrm{Qff}}{\mathrm{CFox}}+2B-\frac{q\mathrm{Nb}\mathrm{tsi}}{2\mathrm{CFox}}+\frac{\mathrm{.Math.o}\mathrm{.Math.si}}{\mathrm{tsi}\mathrm{CFox}}2B$ Eq. 8 // Accounting to Short-Channel-Effects (SCE). There exists a RollOff to the Threshold-Voltage due to DIBL effect, and a RollUp to it as well due to effect of HALO. Both become significant at the lower LGeff value. VT = VTHO + RollOff (LGeff, VD) + RollUp(LGeff, VD) Eq. 9 0$\mathrm{RollOff}\left(\mathrm{LGeff},\mathrm{VD}\right)=-\left[\left({}_0-2B\right)+\mathrm{VD}\right]e^{\frac{-\mathrm{LGeff}}{\mathrm{lc}}}$ Eq. 10 ${}_0=\mathrm{vth}\ln \left(\frac{N^{-}\mathrm{NA}}{{\mathrm{ni}}^2}\right)$ Eq. 11 $\mathrm{lc}=\sqrt{\frac{\mathrm{.Math.o}\mathrm{.Math.si}\mathrm{tox}\mathrm{tsi}}{\mathrm{.Math.o}\mathrm{.Math.ox}}}$ Eq. 12 $\mathrm{RollUp}\left(\mathrm{LGeff},\mathrm{VD}\right)=\left[K-1\right]C2e^{\frac{-\mathrm{LGeff}}{2\mathrm{lc}}}$ Eq. 13 $K=\frac{\mathrm{Wp}+\mathrm{WP\_HALO}}{\mathrm{lc}}\sqrt{\frac{\mathrm{S2}-\mathrm{S1}}{\mathrm{VD}}}$ Eq. 14 S2 = VFG VTHO + 2 B Eq. 15 S1 = VFG VTHOP + 2 P Eq. 16 $\mathrm{VTHOP}={}_{\mathrm{MS}}^f-\frac{q\mathrm{Qff}}{\mathrm{Cof}}+2p-\frac{q\mathrm{Nb}\mathrm{xd}}{\mathrm{CFox}}$ Eq. 17 $p=\mathrm{vth}\ln \left(\frac{\mathrm{NA}}{\mathrm{ni}}\right)$ Eq. 18 $\mathrm{xd}=2\sqrt{\frac{\mathrm{.Math.o}\mathrm{.Math.si}p}{q\mathrm{NA}}}$ Eq. 19 C2 = 2 {square root over ((.sub.02B)(.sub.02B+VD))} Eq. 20 // The Threshold-Voltage of Eq. 9 is function of only 4 unknowns that are: 1. The Carrier concentration of P_Body: NB 2. The Carrier concentration of P_Pocket: NA 3. The carrier concentration of N- region: N- 4. The lateral dimension of P_Pocket: Wp All other parameters are defined in Sec. I & Sec. II. // Sec. IV - Extracting the WGeff that meets the targeted saturated drive current at the targeted Front-Gate bias and VT. Case-1: Drive current depends on Saturation-velocity due to the Short-Channel effect defined when $\frac{\mathrm{vsat}}{e}\mathrm{LGeff}<<\mathrm{VGS}-\mathrm{VT}$ Eq. 21 Then the WGeff is: $\mathrm{WGeff}=\frac{\mathrm{ISat}}{\mathrm{vsat}\mathrm{CFox}\left(\mathrm{VGS}-\mathrm{VT}\right)}$ Eq. 22 0$\mathrm{VKnee}=\frac{\mathrm{vsat}}{e}\mathrm{LGeff}$ Eq. 23 The Isat in Eq. 22 is the targeted Saturation drive current, and The VKnee of Eq. 23 is the device Knee-voltage between linear and saturated drive current. Case-2: Drive current depends on low-field Mobility due to the relatively long LGeff. This occurs when the criteria of Eq. 21 is not met. $\mathrm{WGef}f=\frac{2\mathrm{ISat}\mathrm{LGeff}}{e\mathrm{CFox}{\left(\mathrm{VFG}-\mathrm{VT}\right)}^2}$ Eq. 24 VKnee = VFG VT Eq. 25 Given that the ISat and the VT targets are defined and so is the VGS, and rest of process parameters are known, the WGeff is extracted either from Eq. 22 or from Eq. 24 depending on the magnitude of the LGeff. // Sec. V - Determining the corresponding Body-Current (Ib) for the targeted ISatVFG and VDS. That is II-current. $\mathrm{Ib}=\mathrm{ISat}\left[\frac{}{}\left(\mathrm{VDS}-\mathrm{VKnee}\right)e^{-\frac{\mathrm{lm}}{\mathrm{VDS}-\mathrm{VKnee}}}\right]$ Eq. 26 Ib is extracted from Eq. 26.