A Tunnel Field-Effect Transistor (TFET) device, an isolating layer over a substrate layer, a gate stack above the isolating layer, a source and a drain region over the isolating layer, a channel region underneath the gate stack, and a plurality of nanosheets in the channel region protruding from the source region. Each nanosheet of the plurality of nanosheets includes source region material encapsulated by a narrow band gap material.

A method for manufacturing a gate-all-around TFET device. The method comprises: forming, on a substrate, a channel stack comprising channel layer(s) and sacrificial layer(s) that alternate with each other; forming, on the substrate, a dummy gate astride the channel stack; forming a first spacer at a surface of the dummy gate; etching the sacrificial layer(s) to form recesses on side surfaces of the channel stack; forming second spacers in the recesses, respectively; fabricating a source and a drain separately, where a region for fabricating the source is shielded by a dielectric material when fabricating the drain, and a region for fabricating the drain is shielded by another dielectric material when fabricating the source; etching the dummy gate and the sacrificial layer(s) to form a space for a surrounding gate; and fabricating a surrounding dielectric-metal gate in the space.

Disclosed herein is A structure comprising: a top gate electrode and a bottom gate electrode, a channel layer formed from a channel material with a band gap modulable by electric field, the channel layer being electrically insulated from the top gate electrode and the bottom gate electrode and being located adjacent to at least one layer of a negative capacitance material.

In a general aspect, a quantum control device includes a substrate having a substrate surface. An insulator layer is disposed over the substrate surface and defines a cavity. The insulator layer includes an insulator surface that defines an opening to the cavity. The quantum control device also includes a field-responsive layer over the insulator surface. The field-responsive layer includes a target region that resides over the opening to the cavity. The quantum control device additionally includes a projection extending from the substrate into the cavity and terminating at a tip. The projection is configured to produce an electric field that interacts with a quantum state in the target region. The tip resides in the cavity and configured to concentrate the electric field produced by the projection.

Systems and methods for a quantum computing include a plurality of photonic processing stages, a plurality of heralding-free connections, and circuitry configured to regulate photon flow between adjacent stages such that decisions about stage settings or flow between adjacent stages are free of input from a previous stage. Each heralding-free connection is located between adjacent photonic processing stages. Each photonic processing stage includes at least two of an optical switch, a beam splitter, a waveguide or a photon generator. Methods include transmitting or receiving a plurality of photons via a plurality of heralding-free connections, and regulating photon flow between adjacent stages such that decisions about stage settings or flow between adjacent stages are free of input from a previous stage.

An electronic device includes a first film that is a first layered metal chalcogenide that is single-layered and has a first region and a second region, a second film that overlaps the second region and is a second layered metal chalcogenide that is single-layered or two or more-layered, and an electrode in contact with a laminate of the first film and the second film in the second region.

A vertical tunneling field-effect transistor and a method for its manufacture are provided. According to methods herein disclosed, oppositely doped source and drain regions are formed, and an APAM delta layer is formed in the surface of the transistor substrate, beneath a metal gate, in electrical contact with, e.g., the source region. A dielectric layer intervenes between the substrate surface and the metal gate. An epitaxial cap layer directly over the APAM layer forms a dielectric layer interface with a dielectric layer, which is located between the epitaxial cap layer and the metal gate. A vertical channel is defined for tunneling between the APAM delta layer and an induced conduction channel adjacent to the dielectric layer interface that is formed in operation, and that is in electrical contact with, e.g., the drain region.

A quantum device includes: oscillator groups; circulators; and a transmission path common to the circulators. Each of the oscillator groups includes one or more oscillators having frequency variability. The one or more oscillators are connected to one port of one circulator of the circulators. The one circulator is common to the one or more oscillators. Each of the circulators is arranged on the transmission path. Each of the circulators is configured to: transmit a signal from a first end of the transmission path to the oscillator groups; transmit a signal from any of the oscillator groups to a second end of the transmission path; block a signal from the second end so as not to transmit the signal to the oscillator group; and block a signal from any of the oscillator groups so as not to transmit the signal to the first end.

A method for producing a lateral gate for a semiconductive device, comprising: etching of trenches depositing an electrode laver on the flank of the trenches, and a dielectric material filling. Advantageously, the lateral gate electrostatically controls a distribution of the charge carriers in a metal-oxide-semiconductor (MOS)-type structure, in particular for spin qubit applications.

The technology provided by the present invention makes it possible to obtain desired calculation results efficiently while appropriately avoiding a deadlock in qubit operations performed in a situation where a large number of qubits are arranged. An electron configuration device formed by a quantum computer includes a bus area, an aisle area, and a seat area in a qubit array. In an environment where the seat area and the bus area are connected by the aisle area, the electron configuration device is configured such that a first qubit initially arranged in a predetermined seat area reaches the bus area through the aisle area connected to the seat area and moves through the bus area to a position adjacent to a second qubit to be operated on.