A combination structure of semiconductor deep trench devices includes: a deep trench insulator device, which includes at least one deep trench ring unit, wherein the deep trench ring unit includes: a deep trench ring, a first dielectric side wall layer and a first poly silicon fill region; and a deep trench capacitor device, which includes a plurality of deep trench capacitor units and a cathode, wherein each of the deep trench capacitor units includes: a deep trench hole; a second dielectric side wall layer; and a second poly silicon fill region. The deep trench hole is formed by etching a semiconductor substrate with a same etch process step with the deep trench ring. The first dielectric side wall layer and the second dielectric side wall layer is formed by a same oxide growth process step.

A semiconductor device includes a substrate having a first conductivity type and including a cell region and a termination region. A trench is disposed in the substrate and located in the cell region, and a gate electrode disposed in the trench. A shielding doped region having a second conductivity type is disposed in the substrate and directly below the trench. A buried guard ring having the second conductivity type is disposed in the substrate and located in the termination region. The buried guard ring and the shielding doped region are disposed at the same depth in the substrate. In addition, a junction termination extension structure having the second conductivity type is disposed in the substrate, located directly above and separated from the buried guard ring.

Shielded gate semiconductor devices are disclosed for use in high power applications such as electric vehicles and industrial applications. The devices are formed as mesa (106)/trench (400) structures in which shielded gate electrodes are formed in the trenches. Various trench structures (400, 500, 600, 700) are presented that include tapered portions (401) and end tabs (502, 602, 702, 802) that can be beneficial in managing the distribution of electric charge and associated electric fields. The tapered trenches (400) can be used to increase and stabilize breakdown voltages in a termination region (104) of a semiconductor die (100).

A semiconductor device including a substrate; a first active region disposed in the substrate, the first active region having one or more first type channels and a first plurality of doped regions; a second active region disposed in the substrate, the second active region having one or more second type channels and a second plurality of doped regions, the second active region being physically separated from the first active region by a STI region; an intermediate wiring layer disposed above the substrate, the intermediate wiring layer having a plurality of fingers connected to the first plurality of doped regions and the second plurality of doped regions, respectively; and a metal wiring layer having a source finger and a drain finger, wherein the source finger is connected to a first group of the plurality of fingers, and the drain finger is connected to a second group of the plurality of fingers.

Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (BTBT) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

The present disclosure relates to semiconductor structures and, more particularly, to metal-oxide semiconductor transistors and methods of manufacture. The structure includes: a substrate comprising a drift region and a body region; a gate structure between the drift region and the body region; an insulator material over the gate structure, the drift region and the body region; and an air gap within the insulator material and extending into the drift region.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

The present application discloses a semiconductor transistor structure, which includes: a substrate formed with a well region of a first conductive type, a gate structure being disposed on the substrate; a source/drain region of a second conductive type disposed in the well region of the first conductive type, the source region and the drain region being located on two sides of the gate structure respectively; a contact hole formed at a position corresponding to the source/drain region; and a conductive metal filled in the contact hole, the bottom of the contact hole being implanted with impurity ions for decreasing the contact resistance of the contact hole, and the impurity ion concentration at a peripheral region where the bottom of the contact hole comes into contact with the source/drain region being lower than the impurity ion concentration at a middle region.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

A semiconductor structure includes a supporting substrate, a buried layer, a growth substrate, a buffer layer, and a heterojunction structure layer that are sequentially stacked; a plurality of recesses are disposed on a side, away from the supporting substrate, of the growth substrate, and the buffer layer completely covers a surface of the growth substrate. In the present disclosure, the recesses are disposed in the growth substrate, so that a parasitic circuit formed in the growth substrate caused by a radio frequency signal may be blocked, to reduce a disturbance effect of the growth substrate, thereby reducing an RF loss; and the buffer layer is formed, by using epitaxial lateral overgrowth, in the recesses of the growth substrate, so that dislocation density in an epitaxial layer may be greatly reduced, to improve crystal quality, thereby improving characteristics such as electron mobility, breakdown voltage, and leakage current of a device.