According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

Provided is a semiconductor device comprising a diode portion, comprising: a plurality of trench portions provided at a front surface of a semiconductor substrate; a drift region of a first conductivity type provided on the semiconductor substrate; an anode region of a second conductivity type provided above the drift region in the diode portion; a first plug region of the second conductivity type provided above the drift region in the diode portion, which has a doping concentration higher than a doping concentration of the anode region; a front surface side electrode provided above the semiconductor substrate; and an interlayer dielectric film provided above a mesa portion provided between the plurality of trench portions; wherein the anode region is connected to the front surface side electrode on side surfaces of the plurality of trench portions.

A semiconductor device includes a chip with a main surface, featuring a first conductivity type base region. A trench gate structure penetrates the base region, while a second conductivity type emitter region is formed along the trench gate structure on the surface. Between the bottom of the base region and the emitter region, a higher impurity concentration in-base region is present. An insulating film covers the main surface, featuring a connection hole that exposes part of the emitter region at a distance from the in-base region. A connection electrode is positioned in the connection hole, electrically connecting the base and emitter regions.

A semiconductor module includes an IGBT device, and a MISFET device that composes a parallel circuit together with the IGBT device. The semiconductor module generates a drain current of the MISFET device in a voltage range less than a built-in voltage of the IGBT device and generates a collector current of the IGBT device and a drain current of the MISFET device in a voltage range equal to or more than the built-in voltage.

An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor. In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.

A device is disclosed that includes a first transistor, a second transistor, and a first PODE device. The second transistor is electrically coupled to the first transistor. The first PODE device is adjacent to a drain/source region of the second transistor. A control end of the first PODE device is electrically coupled to a drain/source end of the second transistor.

A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is level with a top surface of the substrate, removing an upper portion of the first isolation region to form a recess, depositing a gate dielectric layer over the first isolation region, forming a gate electrode layer over the gate dielectric layer and patterning the gate electrode layer to form a gate electrode region, wherein a first portion of the gate electrode region is vertically aligned with the first isolation region and a second portion of the gate electrode region is formed over the substrate, and where a top surface of the first portion is lower than a top surface of the second portion.

Apparatus and methods for providing variable regulated voltages are disclosed. Variable voltage control elements can adjust a regulated voltage provided by a single voltage regulator, thereby providing a variable regulated voltage. The regulated voltage can be used in a variety of applications, for example, as a bias voltage for a power amplifier.

Disclosed are CMOS-based devices for switching radio frequency (RF) signals and methods for biasing such devices. In certain RF devices such as mobile phones, providing different amplification modes can yield performance advantages. For example, a capability to transmit at low and high power modes typically results in an extended battery life, since the high power mode can be activated only when needed. Switching between such amplification modes can be facilitated by one or more switches formed in an integrated circuit and configured to route RF signal to different amplification paths. In certain embodiments, such RF switches can be formed as CMOS devices, and can be based on triple-well structures. In certain embodiments, an isolated well of such a triple-well structure can be provided with different bias voltages for on and off states of the switch to yield desired performance features during switching of amplification modes.

A method for manufacturing a semiconductor device is provided. The method includes operations below. First, an epitaxial layer is formed on a substrate. Then, a trench is formed in the epitaxial layer. Then, a first dielectric layer and a shield layer are formed in the trench, in which the shield layer is embedded within the first dielectric layer. Then, a spacer layer is formed in the trench and on the first dielectric layer. Finally, a second dielectric layer and a gate are formed in the trench and on the spacer layer, and a source is formed in the epitaxial layer surrounding the trench, in which the gate is embedded within the second dielectric layer, and the source surrounds the gate.