An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

An IGBT device includes a drift region of a first doping type; a plurality of pillar regions of the second doping type, disposed at intervals in the lateral direction within the drift region; and a transition layer of the first doping type, connected under the pillar region. The thickness of the transition layer is larger than 2 microns and less than or equal to 11 microns, and the doping concentration of the transition layer ranges from larger than or equal to 2.410.sup.14/cm.sup.3 to less than or equal to 2.410.sup.16/cm.sup.3, in order to solve the technical problem of a large turn-off energy loss due to the tail current of the conventional SJ-IGBT device in the turn-off stage.

A method of manufacturing a superjunction silicon carbide semiconductor device is provided, enabling a reduction of the number of times a combination of epitaxial growth and ion implantation for forming a parallel pn structure is performed. In the method of manufacturing the superjunction silicon carbide semiconductor device, forming an epitaxial layer 2a, 2b of a second conductivity type on a front surface of a silicon carbide semiconductor substrate 1 of a first conductivity type and selectively forming semiconductor regions 4a, 4b of the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated multiple times, thereby forming the parallel pn structure.

A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

A semiconductor device has a substrate and semiconductor layer formed over the substrate. The semiconductor layer has a first conductivity type. A trench is formed through the semiconductor layer. A semiconductor material having a second conductivity type is deposited over a side surface of the trench by vapor phase deposition or plasma doping. The semiconductor material is diffused into the semiconductor layer to form a first column of semiconductor material having the second conductivity type within the semiconductor layer. A first insulating layer is formed over the side surface of the trench. A body region is formed within the semiconductor layer. A source region is formed within the body region. A gate region is formed within the body region. A second insulating layer is formed over the trench. A third insulating layer is formed over the second insulating layer. A conductive layer is formed over the third insulating layer.

A semiconductor device has a substrate and semiconductor layer formed over the substrate. The semiconductor layer has a first conductivity type. A trench is formed through the semiconductor layer. An epitaxial layer having a second conductivity type is formed over a surface of the semiconductor layer and a side surface of the trench. The epitaxial layer is diffused into the semiconductor layer to form a first column of semiconductor material having the second conductivity type within the semiconductor layer. A first insulating layer is formed over the side surface of the trench. A body region is formed within the semiconductor layer. A source region is formed within the body region. A gate region is formed within the body region. A second insulating layer is formed over the trench. A third insulating layer is formed over the second insulating layer. A conductive layer is formed over the third insulating layer.

The present disclosure provides a split gate MOSFET and a manufacturing method thereof. An epitaxy layer with a first conductivity type is formed on a substrate. A plurality of trenches are formed in the epitaxy layer. Impurities with a second conductive type is implanted and driven to the trenches to form a plurality of first doping areas. Since the first doping areas and none-doping areas of the epitaxy layer are alternately arranged with each other, and the first conductive type and the second conductive type are different conductivity types selected from P type or N type, the split gate MOSFET including the super junction structure is manufactured, and the advantages of simplifying manufacturing process, reducing cost and greatly reducing the on-resistance are achieved.

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.