A semiconductor device having a high cutoff resistance capable of suppressing local current/electric field concentration and current concentration at a chip termination portion due to an electric field variation between IGBT cells due to a shape variation and impurity variation during manufacturing. The semiconductor device is characterized by including an emitter electrode formed on a front surface of a semiconductor substrate via an interlayer insulating film, a collector electrode formed on a back surface of the semiconductor substrate, a first semiconductor layer of a first conductivity type in contact with the collector electrode, a second semiconductor layer of a second conductivity type, a central area cell, and an outer peripheral area cell located outside the central area cell.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

A semiconductor device includes a substrate having a first conductivity type and including a cell region and a termination region. A trench is disposed in the substrate and located in the cell region, and a gate electrode disposed in the trench. A shielding doped region having a second conductivity type is disposed in the substrate and directly below the trench. A buried guard ring having the second conductivity type is disposed in the substrate and located in the termination region. The buried guard ring and the shielding doped region are disposed at the same depth in the substrate. In addition, a junction termination extension structure having the second conductivity type is disposed in the substrate, located directly above and separated from the buried guard ring.

An RC IGBT includes, in a single chip, an active region configured to conduct both a forward load current and a reverse load current between a first load terminal at a front side of a semiconductor body of the RC IGBT and a second load terminal at a back side of the semiconductor body. The active region is separated into at least an IGBT-only region and an RC IGBT region. At least 90% of the IGBT-only region is configured to conduct, based on a first control signal, only the forward load current. At least 90% of the RC IGBT region is configured to conduct the reverse load current and, based on a second control signal, the forward load current.

A semiconductor device is proposed. The semiconductor device includes trenches extending into a semiconductor body from a first main surface. A first group of the trenches includes a gate electrode. A second group of the trenches includes a source electrode, the source electrode being subdivided into at least a first part and a second part. A conductance per unit length of the first part along a longitudinal direction of the source electrode is smaller than a conductance per unit length of the second part along the longitudinal direction of the source electrode, the second part being electrically coupled to a source contact area via the first part. A mesa region bounded by a trench of the first group and a trench of the second group includes a source region electrically connected to the source contact area.

A transistor structure with a multi-layer field plate and related methods are disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a field plate on the thicker portion of the dielectric layer.

A transistor can include a plurality of source regions and a plurality of drain regions arranged in an alternating manner, with each of the source regions and the drain regions being implemented as a first type active region, and a plurality of gate structures implemented relative to the source regions and the drain regions such that application of a voltage to each gate structure results in formation of a conductive channel between a respective pair of source and drain regions. The transistor can further include a body region configured to provide the respective conductive channel upon the application of the voltage to the corresponding gate structure, with the body region being implemented as a second type active region. The transistor can further include a recessed region defined by an end of each drain region and one or both of the gate structures adjacent to the drain region.

Various implementations described herein are directed to a device having a skew cell architecture with multiple diffusion regions including P-type diffusion regions disposed between N-type diffusion regions. The device may have power rails including a voltage supply rail disposed between ground rails. The device may have poly-gate rails disposed between the ground rails. The poly-gate rails may be cut to provide an open space between at least one N-type diffusion region and at least one P-type diffusion region.

To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

A semiconductor device includes a semiconductor layer; a trench formed in the semiconductor layer and including a side wall, an insulation layer formed on the semiconductor layer; and a gate electrode arranged in the trench. The insulation layer includes a gate insulation portion located between the semiconductor layer and the gate electrode, and covering the side wall of the trench. The gate electrode includes a first conductive portion contacting the gate insulation portion, and a second conductive portion including a side surface contacting the first conductive portion. The first conductive portion is formed from polysilicon, and the second conductive portion is formed from metal.