Patent classifications
H10D62/134
Repeated emitter design for achieving scalable lateral PNP behavior
A semiconductor device is described herein. The semiconductor device includes a substrate and a collector region in the substrate. The semiconductor device also includes a plurality of emitter regions in the substrate, each of the plurality emitter regions separate from each other, wherein the plurality of emitter regions is disposed in an area bounded by the collector region.
BIPOLAR TRANSISTOR
A device includes a bipolar transistor. The bipolar transistor includes: a collector region, a base region, and an emitter region. A first metallization is in contact with the emitter region, a second metallization is in contact with the base region, and a third metallization is in contact with the collector region. A first connection element is coupled to the first metallization and has dimensions, in a plane of the interface between the first metallization and the connection element, greater than dimensions of the first metallization. A second connection element is coupled to the second metallization and passes through spacers, which at least partially cover the second metallization, surrounding the emitter region. A third connection element is coupled to the third metallization and passes through spacers, which at least partially cover the third metallization, surrounding the base region.
SEMICONDUCTOR DEVICE
A semiconductor device is provided. The semiconductor includes at least one of a well area in a substrate and having a first conductivity-type; impurity-implanted areas in the well, and having a second conductivity-type different from the first conductivity-type and arranged in a first direction, a first fin structure on the impurity-implanted area and having the second conductivity-type, wherein the first fin structure includes first semiconductor patterns and first sacrificial patterns alternately stacked; a first contact on the first fin structure; a first epitaxial pattern on the well area and having the first conductivity-type; and a second contact on the first epitaxial pattern.
Heterojunction bipolar transistors with terminals having a non-planar arrangement
Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.
Horizontal current bipolar transistors with improved breakdown voltages
A horizontal current bipolar transistor comprises a substrate of first conductivity type, defining a wafer plane parallel to said substrate; a collector drift region above said substrate, having a second, opposite conductivity type, forming a first metallurgical pn-junction with said substrate; a collector contact region having second conductivity type above said substrate and adjacent to said collector drift region; a base region comprising a sidewall at an acute angle to said wafer plane, having first conductivity type, and forming a second metallurgical pn-junction with said collector drift region; and a buried region having first conductivity type between said substrate and said collector drift region forming a third metallurgical pn-junction with the collector drift region. An intercept between an isometric projection of said base region on said wafer plane and an isometric projection of said buried region on said wafer plane is smaller than said isometric projection of said base region.
METHOD FOR CREATING THE HIGH VOLTAGE COMPLEMENTARY BJT WITH LATERAL COLLECTOR ON BULK SUBSTRATE WITH RESURF EFFECT
Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.
LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE
A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE
A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
Operation of double-base bipolar transistors with additional timing phases at switching transitions
Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate. A diode prevents reverse turn-on while negative base drive is being applied.
Bipolar junction transistor layout
A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.