An IGBT includes, in a single chip, an active region configured to conduct a forward load current between first and second load terminals at different sides of a semiconductor body. The active region is separated into at least first and second IGBT regions. At least 90% of the first IGBT region is configured to conduct, based on a first control signal, the forward load current. At least 90% of the second IGBT region is configured to conduct, based on a second control signal, the forward load current. A first MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the first IGBT region divided by a total lateral area of first IGBT region. A second MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the second IGBT region divided by a total lateral area of the second IGBT region. The second MOS-channel-conductivity-to-area-ratio amounts to less than 80% of the first MOS-channel-conductivity-to-area-ratio.

A molding is formed by laminating an aggregate of SiC and a paste containing Si and C powders on an epitaxial layer of SiC formed on a support substrate of SiC to form an intermediate sintered body in which polycrystalline SiC is produced from the Si and C powders by reaction sintering, free Si is carbonized to SiC to form a sintered body layer, and the support substrate is removed from the epitaxial layer to form a semiconductor substrate in which the epitaxial layer and the sintered body layer are laminated.

We herein describe a semiconductor device comprising a first element portion formed on a substrate, the first element portion being an operating region of an insulated gate bipolar transistor (IGBT) and a second element portion formed on the substrate, the second element portion being an operating region of a diode. The first element portion comprises a first collector region of a second conductivity type, a drift region of a first conductivity type located over the first collector region, and formed by the semiconductor substrate, a first body region of a first conductivity type located over the drift region, a second body region of a second conductivity type located over the drift region, at least one first contact region of a first conductivity type located above the second body region and having a higher doping concentration compared to the first body region, at least one second contact region of a second conductivity type located laterally adjacent to the at least one first contact region, the at least one second contact region having a higher doping concentration than the second body region, a first plurality of trenches extending from a surface through the second body region of a second conductivity type into the drift region wherein the at least one first contact region adjoins at least one of the plurality of trenches so that, in use, a channel region is formed along said at least one trench of the first plurality of trenches and within the body region of a second conductivity type. A first trench of the first plurality of trenches is laterally spaced from a second trench of the first plurality of trenches by a first distance. The second element portion comprises a second collector region of a second conductivity type, the drift region of a first conductivity type located over the second collector region, a third body region of a second conductivity type located over the drift region, a second plurality of trenches extending from a surface through the third body region into the drift region. A first trench of the second plurality of trenches is laterally spaced from a second trench of the second plurality of trenches by a second distance, and the first distance is larger than the second distance. The semiconductor device further comprises a first terminal contact, wherein the first terminal contact is electrically connected to the at least one first contact region of a first conductivity type and the body region of a second conductivity type and a second terminal contact, wherein the second terminal contact is electrically connected to the first collector region and the second collector region.

A method of forming a layered, high power vertical insulated-gate switch uses an n-type substrate. A p-well is formed by implantation in the top surface of the substrate followed by implanting n-type dopants in the p-well to form n+ source regions. Trenched gates are formed extending through the n+ source regions and into the p-well. The wafer is transferred to a carrier and the bottom surface of the wafer substrate is thinned by CMP. An n-buffer layer is then epitaxially grown on the bottom surface using low temperature epitaxy (LTE). The low temperature does not substantially diffuse the dopants in the overlying regions. A bottom p+ layer is then formed by LTE. Anode and cathode metal electrodes are then formed. The n-buffer layer and p+ layers can be precisely formed for optimal efficiency and the LTE maintains the dopant profiles of the overlying regions.

A method of producing a semiconductor device includes providing a semiconductor body having a front side 10-1 and a back side, wherein the semiconductor body includes a drift region having dopants of a first conductivity type and a body region having dopants of a second conductivity type complementary to the first conductivity type, a transition between the drift region and the body region forming a pn-junction. The method further comprises: creating a contact groove in the semiconductor body, the contact groove extending into the body region along a vertical direction pointing from the front side to the back side; and filling the contact groove at least partially by epitaxially growing a semiconductor material within the contact groove, wherein the semiconductor material has dopants of the second conductivity type.

A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C). The semiconductor body region isolates the source region from the drift region and includes a reduced band gap zone comprising a second semiconductor material (M2) having a second band gap that is smaller than the first band gap, wherein the reduced band gap zone is arranged in the semiconductor body region such that the reduced band gap zone and the source region exhibit, in a cross-section along a vertical direction (Z), at least one of a common lateral extension range (LR) along a first lateral direction (X) and a common vertical extension range (VR) along the vertical direction (Z).

A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.

A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.

A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.

A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.