Patent classifications
H10D62/192
SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING A SEMICONDUCTOR DEVICE
According to an embodiment, the semiconductor device (100) comprises a semiconductor body (1) with a first side (10) and a second side (20) opposite to the first side. The semiconductor device further comprises a first thyristor structure (I) and a second thyristor structure (II). The second thyristor structure is arranged laterally beside the first thyristor structure. Each of the first and the second thyristor structure comprises a first base region (11a, 11b) at the first side and agate electrode (1a, 1b) on the first side adjoining the assigned first base region. The first base regions of the two thyristor structures are regions of the semiconductor body and are of the same conductivity type. The gate electrodes of the thyristor structures are individually and independently electrically contactable.
SOI INTEGRATED CIRCUIT EQUIPPED WITH A DEVICE FOR PROTECTING AGAINST ELECTROSTATIC DISCHARGES
A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.
On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges
The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.
Two-Transistor SRAM Semiconductor Structure and Methods of Fabrication
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication
A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby.
Two-transistor SRAM semiconductor structure and methods of fabrication
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
Bidirectional thyristor device with asymmetric characteristics
Bidirectional thyristor device comprising a semiconductor body extending in a vertical direction between a first main surface and a second main surface opposite the first main surface, a first main electrode arranged on the first main surface, and a second main electrode arranged on the second main surface, is specified, wherein the semiconductor body comprises a first base layer of a first conductivity type, a second base layer of the first conductivity type, and a third base layer of a second conductivity type different than the first conductivity type arranged between the first base layer and the second base layer. The first main electrode acts as a cathode for a first thyristor functional element and as an anode for a second thyristor functional element of the bidirectional thyristor device. The bidirectional thyristor device is configured asymmetrically with respect to the first thyristor functional element and the second thyristor functional element.