The present invention discloses a field effect transistor device with a blocking region, which aims to address the problem of short channel effects of a field effect transistor in the prior art. The field effect transistor device includes an active layer, the active layer including a source region, a drain region and a channel region located between the source region and the drain region, wherein the channel region is provided with a carrier blocking region. The carrier blocking region serves to block carriers moving from the source region to the drain region when the device is turned off.

Provided are a display base plate and a preparation method thereof and a display apparatus, belonging to the technical field of display devices. The display base plate comprises a substrate, and a light-emitting diode and a driving circuit which are patterned and arranged on one side of the substrate, and the light-emitting diode comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are stacked; and the driving circuit is respectively connected with the first semiconductor layer and the second semiconductor layer, and is used for driving the light-emitting diode to emit light. By the display base plate and the preparation method thereof and the display apparatus provided by the embodiment of the application, the difficulty of integrating the driving circuit and the light-emitting diode in the display base plate can be reduced, so that a preparation process of the display base plate is simpler.

A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a liner layer and an isolation structure surrounding the fin structure. The structure also includes a gate dielectric layer formed over the fin structure and the isolation structure. The structure also includes a gate structure formed over the gate dielectric layer. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The fin structure includes a protruding portion laterally extending over the liner layer.

A light emitting device including an insulation unit, a light emitting region including first, second, and third LED stacks each including first and second conductivity type semiconductor layers, a first pillar electrically connected to the first conductivity type semiconductor layers of the first, second, and third LED stacks, and a second pillar, a third pillar, and a fourth pillar electrically connected to the second conductivity type semiconductor layers of the first, second, and third LED stacks, respectively, an intermediate first connector and a lower first connector respectively electrically connecting the first conductivity type semiconductor layers of the second LED stack and the third LED stack to the first pillar, in which the insulation unit have four corners, and the first, second, third, and fourth pillars are disposed near the four corners covering a side surface of the insulation unit, respectively.

A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.

Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.

The present invention relates to an array substrate, which comprises: a display region and a drive circuit region; the drive circuit region comprises GOA units, the GOA unit comprising a substrate, a gate electrode layer, an insulation layer, an active layer and a source/drain electrode layer, and the drive circuit region further comprises a gate wire connecting to the gate electrode layer, and a source/drain layer wire at the same layer with the source/drain electrode layer, wherein the area between the portions of the gate wire and the source/drain layer wire which intercross with each other is only formed with the insulation layer. The invention further relates to a manufacturing method of an array substrate and a display apparatus comprising the array substrate.

A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.

A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction.