Patent classifications
H10D62/882
NEGATIVE CAPACITANCE TOPOLOGICAL QUANTUM FIELD-EFFECT TRANSISTOR
Disclosed herein is A structure comprising: a top gate electrode and a bottom gate electrode, a channel layer formed from a channel material with a band gap modulable by electric field, the channel layer being electrically insulated from the top gate electrode and the bottom gate electrode and being located adjacent to at least one layer of a negative capacitance material.
Quantum control devices and methods
In a general aspect, a quantum control device includes a substrate having a substrate surface. An insulator layer is disposed over the substrate surface and defines a cavity. The insulator layer includes an insulator surface that defines an opening to the cavity. The quantum control device also includes a field-responsive layer over the insulator surface. The field-responsive layer includes a target region that resides over the opening to the cavity. The quantum control device additionally includes a projection extending from the substrate into the cavity and terminating at a tip. The projection is configured to produce an electric field that interacts with a quantum state in the target region. The tip resides in the cavity and configured to concentrate the electric field produced by the projection.
Semiconductor device and method for forming the same
A plasma enhanced chemical vapor deposition (PECVD) method includes loading a wafer having a magnetic layer thereon into a processing chamber equipped with a radio frequency (RF) system, introducing an aromatic hydrocarbon precursor into the processing chamber, and turning on an RF source of the RF system to decompose the aromatic hydrocarbon precursor into active radicals at a frequency greater than about 1000 Hz to form a graphene layer over the magnetic layer.
Semiconductor device including two-dimensional material
A semiconductor device according to an embodiment may include a substrate, an adhesive layer, and a semiconductor layer. The semiconductor layer includes a 2D material having a layered structure. The adhesive layer is interposed between the substrate and the semiconductor layer, and has adhesiveness to a 2D material.
SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF
A semiconductor device includes a substrate, a first dielectric layer, a channel layer and source/drain electrodes. The first dielectric layer is over the substrate. The channel layer is over the first dielectric layer. Source/drain electrodes are over the channel layer. The source/drain electrodes comprise a 2D semimetal material. The channel layer comprises a 2D semiconductor material interfacing the 2D semimetal material of the source/drain electrodes.
DOPING ACTIVATION AND OHMIC CONTACT FORMATION IN A SiC ELECTRONIC DEVICE, AND SiC ELECTRONIC DEVICE
A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500 C. and 2600 C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.
Thin film transistor including a stacked multilayer graphene active layer
A semiconductor device includes a graphene film disposed on a substrate and formed of atomic layers of graphene that are stacked, a source electrode and a drain electrode disposed on the graphene film, and a gate electrode disposed on the graphene film between the source electrode and the drain electrode with a gate insulator film interposed between the gate electrode and the graphene film, wherein a first number of the atomic layers of the graphene film in a source region where the source electrode is located and a drain region where the drain electrode is located is greater than a second number of the atomic layers of the graphene film in a channel region where the gate electrode is located.
Black phosphorus-two dimensional material complex and method of manufacturing the same
Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.
CONDUCTIVE MATERIAL DEPOSITION ON SEMICONDUCTOR WITH PHASE TRANSITION AND OHMIC CONTACT IN SITU
A method for a photon induced conductive material deposition on a substrate is provided. The method includes steps as follows: preparing a first solution comprising metalate, metal ions, or combinations thereof; preparing a first suspension comprising nanoparticles, a light sensitive reducing agent, an electron providing solvent, or combinations thereof; mixing the first solution and the first suspension to form a first reagent on a first substrate; and emitting a light beam provided by a light source and focusing the same onto the first reagent kept on a first region of the first substrate, so as to form a mechanically rigid conductive deposition in contact with the first substrate in a focus point of the light source, wherein the first substrate has a second region exposed to surrounding gas or an air environment.
Graphene layer transfer
A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene.