A semiconductor device includes a first electrode, a first conductive part, a semiconductor part, a second conductive part, a gate electrode and an insulating part. The first conductive part includes at least one of a metal, a metal oxide, or a metal nitride. The at least one of the metal, the metal oxide, or the metal nitride includes at least one selected from the group consisting of Ti, Ta, W, Cr, and Ru. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first conductive part has a Schottky contact with the first semiconductor region. The second conductive part has a Schottky contact with the second semiconductor region. The second conductive part includes at least one selected from the group consisting of Pt, Ni, Ir, Pd, Au, and Co.

The present disclosure relates to a power semiconductor device (100) comprising a silicon carbide semiconductor. SiC. structure (110) comprising a SiC epilayer (112), at least one ohmic contact (120) formed on a first main surface (114) of the SiC structure (110), and at least Schottky barrier contact (130) formed on a second main surface (116) of the SiC structure (110). The at least one Schottky barrier contact (130) comprises a metal layer (136) and a carbon group interlayer (134) arranged between the metal layer (136) and the second main surface (116) of the SiC structure (110). 15 The present disclosure relates to a Schottky barrier diode (400). a vertical field effect transistor, such as a power MOSFET (500), and a method for manufacturing a power semiconductor device (100).

A GaN-based semiconductor device includes a substrate; a GaN channel layer disposed on the substrate; a AlGaN layer disposed on the GaN channel layer; a p-GaN gate layer disposed on the AlGaN layer; and a nitrogen-rich TiN hard mask layer disposed on the p-GaN gate layer. The nitrogen-rich TiN hard mask layer has a nitrogen-to-titanium (N/Ti) ratio that is greater than 1.0. A gate electrode layer is disposed on the nitrogen-rich TiN hard mask layer.

Ions are implanted into a first wafer through a top side, generating an ion damaged layer underneath the substrate film of the first wafer. A stress inducing layer is applied on a surface on the top side of the first wafer on one of the ion implanted side and the opposite side. The substrate film is separated from the first wafer at the ion damaged layer. the separated substrate film is bonded to a second wafer at a surface on one of a first side and a second side that this opposite of the first side of the second wafer to form an engineered wafer.

A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

Some embodiments relate to an integrated device, including a semiconductor film accommodating a two-dimensional carrier gas (2DCG) over a substrate; a first source/drain electrode over the semiconductor film; a second source/drain electrode over the semiconductor film; a semiconductor capping structure between the first source/drain electrode and the second source/drain electrode; a first gate overlying the semiconductor capping structure and between the first source/drain electrode and the second source/drain electrode in a first direction; a first helping gate overlying the semiconductor capping structure and bordering the first gate, wherein the first helping gate and the second source/drain electrode are arranged in a line extending in a second direction transverse to the first direction.

A semiconductor device includes: a gate electrode including a junction portion forming a Schottky junction with a barrier layer; a projecting portion including first and second gate field plates and projecting from the junction portion; and an insulating layer including first and second sidewalls. An angle formed between a highest position of a bottom surface of the first gate field plate and a main surface of a substrate, viewed from the first position, is a second elevation angle. An angle formed between an end on the drain electrode side of a lowest portion of a bottom surface of the second gate field plate and the main surface, viewed from the first position, is a third elevation angle. The second elevation angle is larger than the third elevation angle. The bottom surface of the second gate field plate includes an inclined surface where a distance from the barrier layer monotonically increases.

A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.

In an embodiment, a Group III nitride-based transistor device is provided that includes a Group III nitride-based body and a p-type Schottky gate including a metal gate on a p-doped Group III nitride structure. The p-doped Group III nitride structure includes an upper p-doped GaN layer in contact with the metal gate and having a thickness d.sub.1, a lower p-doped Group III nitride layer having a thickness d.sub.2 and including p-doped GaN that is arranged on and in contact with the Group III nitride-based body, and at least one p-doped Al.sub.xGa.sub.1-xN layer arranged between the upper p-doped GaN layer and the lower p-doped Group III nitride layer, wherein 0<x<1. The thickness d.sub.2 of the lower p-doped Group III nitride layer is larger than the thickness d.sub.1 of the upper p-doped GaN layer.

A semiconductor device includes a semiconductor layer, a gate structure, a control-source electrode plate, and a drain electrode. The semiconductor layer has a channel region. The gate structure has a surface to contact the semiconductor layer, in which the gate structure overlaps the channel region of the semiconductor layer along a direction perpendicular to the surface of the gate structure. The control-source electrode plate is in contact with the semiconductor layer, in which the control-source electrode plate covers the gate structure and the channel region of the semiconductor layer along the direction perpendicular to the surface of the gate structure. The drain electrode is in contact with the semiconductor layer.