GALLIUM NITRIDE SEMICONDUCTOR DEVICE

Abstract

A GaN-based semiconductor device includes a substrate; a GaN channel layer disposed on the substrate; a AlGaN layer disposed on the GaN channel layer; a p-GaN gate layer disposed on the AlGaN layer; and a nitrogen-rich TiN hard mask layer disposed on the p-GaN gate layer. The nitrogen-rich TiN hard mask layer has a nitrogen-to-titanium (N/Ti) ratio that is greater than 1.0. A gate electrode layer is disposed on the nitrogen-rich TiN hard mask layer.

Claims

1. A GaN-based semiconductor device, comprising: a substrate; a GaN channel layer disposed on the substrate; a AlGaN layer disposed on the GaN channel layer; a p-GaN gate layer disposed on the AlGaN layer; a nitrogen-rich TiN hard mask layer disposed on the p-GaN gate layer, wherein the nitrogen-rich TiN hard mask layer has a nitrogen-to-titanium (N/Ti) ratio that is greater than 1.0; and a gate electrode layer disposed on the nitrogen-rich TiN hard mask layer.

2. The GaN-based semiconductor device according to claim 1 further comprising: a buffer layer on the substrate, wherein the buffer layer is disposed between the substrate and the GaN channel layer.

3. The GaN-based semiconductor device according to claim 2, wherein the buffer layer comprises AlN or GaN and has a thickness of about 3-5 m.

4. The GaN-based semiconductor device according to claim 1, wherein the GaN channel layer has a thickness of 200-400 nm.

5. The GaN-based semiconductor device according to claim 1, wherein the AlGaN layer has a thickness of 10-14 nm.

6. The GaN-based semiconductor device according to claim 1, wherein the p-GaN gate layer has a thickness of 60-100 nm.

7. The GaN-based semiconductor device according to claim 1, wherein the gate electrode layer comprises a TiN bottom layer, a AlCu middle layer, and a TiN top layer, wherein the TiN bottom layer is in direct contact with the nitrogen-rich TiN hard mask layer.

8. The GaN-based semiconductor device according to claim 1, wherein the N/Ti ratio of the nitrogen-rich TiN hard mask layer is equal to or greater than 1.04.

9. The GaN-based semiconductor device according to claim 1 further comprising: a Al.sub.2O.sub.3 passivation layer covering a sidewall of the p-GaN gate layer, a sidewall of the nitrogen-rich TiN hard mask layer, and a top surface of the AlGaN layer.

10. The GaN-based semiconductor device according to claim 9 further comprising: an insulating layer disposed on the Al.sub.2O.sub.3 passivation layer.

11. A method for fabricating a GaN-based semiconductor device, comprising: providing a substrate; forming a GaN channel layer on the substrate; forming a AlGaN layer on the GaN channel layer; forming a p-GaN gate layer on the AlGaN layer; forming a nitrogen-rich TiN hard mask layer on the p-GaN gate layer, wherein the nitrogen-rich TiN hard mask layer has a nitrogen-to-titanium (N/Ti) ratio that is greater than 1.0; and forming a gate electrode layer on the nitrogen-rich TiN hard mask layer.

12. The method according to claim 11 further comprising: forming a buffer layer on the substrate, wherein the buffer layer is disposed between the substrate and the GaN channel layer.

13. The method according to claim 12, wherein the buffer layer comprises AlN or GaN and has a thickness of 3-5 m.

14. The method according to claim 11, wherein the GaN channel layer has a thickness of 200-400 nm, the AlGaN layer has a thickness of 10-14 nm, and the p-GaN gate layer has a thickness of 60-100 nm.

15. The method according to claim 11, wherein the nitrogen-rich TiN hard mask layer is formed on the p-GaN gate layer by sputtering at a direct current (DC) power that is equal to or greater than 4000 W.

16. The method according to claim 11, wherein the nitrogen-rich TiN hard mask layer is formed on the p-GaN gate layer by sputtering at a DC power of 7500-8500 W.

17. The method according to claim 11, wherein the gate electrode layer comprises a TiN bottom layer, a AlCu middle layer, and a TiN top layer, wherein the TiN bottom layer is in direct contact with the nitrogen-rich TiN hard mask layer.

18. The method according to claim 11, wherein the N/Ti ratio of the nitrogen-rich TiN hard mask layer is equal to or greater than 1.04.

19. The method according to claim 11 further comprising: forming a Al.sub.2O.sub.3 passivation layer covering a sidewall of the p-GaN gate layer, a sidewall of the nitrogen-rich TiN hard mask layer, and a top surface of the AlGaN layer.

20. The method according to claim 19 further comprising: forming an insulating layer on the Al.sub.2O.sub.3 passivation layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 is a schematic, partial cross-sectional view of a GaN-based semiconductor device according to an embodiment of the present invention.

[0027] FIG. 2 is a flow chart of a fabrication method of a GaN-based semiconductor device.

DETAILED DESCRIPTION

[0028] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

[0029] Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

[0030] Please refer to FIG. 1, which is a partial cross-sectional view of a GaN-based semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, a GaN-based semiconductor device 1 includes a substrate 100, for example, a silicon substrate with a (111) crystal plane, but not limited thereto. According to an embodiment of the present invention, the GaN-based semiconductor device 1 may be a p-GaN/AlGaN/GaN high electron mobility transistor (HEMT) device.

[0031] According to an embodiment of the present invention, a buffer layer 102 and a GaN channel layer 104 are formed on the substrate 100. The buffer layer 102 and the GaN channel layer 104 may be formed using an epitaxial process, such as a metal organic chemical vapor deposition (MOCVD) process or a molecular beam epitaxy (MBE) process, but not limited thereto.

[0032] According to an embodiment of the present invention, the buffer layer 102 may include AlN or GaN. According to an embodiment of the present invention, the thickness of the buffer layer 102 is, for example, 3-5 m, but not limited thereto. According to an embodiment of the present invention, the thickness of the GaN channel layer 104 is, for example, 200-400 nm, but is not limited thereto.

[0033] According to an embodiment of the present invention, the GaN-based semiconductor device 1 further includes an AlGaN layer 106 disposed on the GaN channel layer 104. According to an embodiment of the present invention, the thickness of the AlGaN layer 106 is, for example, 10-14 nm, but not limited thereto.

[0034] According to an embodiment of the present invention, a two-dimensional electron gas (2DEG) 106a is formed at the interface between the AlGaN layer 106 and the GaN channel layer 104. The two-dimensional electron gas 106a is a very thin conductive layer with highly mobile and highly concentrated charge carriers.

[0035] According to an embodiment of the present invention, the GaN-based semiconductor device 1 further includes a patterned p-GaN gate layer 108 disposed on the AlGaN layer 106. According to an embodiment of the present invention, the p-GaN gate layer 108 can also be formed by an epitaxial process, for example, metal organic chemical vapor deposition process or molecular beam epitaxy, but not limited thereto. According to an embodiment of the present invention, the thickness of the p-GaN gate layer 108 is, for example, 60-100 nm, but not limited thereto.

[0036] According to an embodiment of the present invention, as shown in the partial enlarged view in FIG. 1, the GaN-based semiconductor device 1 further includes a patterned nitrogen-rich TiN hard mask layer 110 disposed on the p-GaN gate layer 108, wherein the nitrogen-to-titanium (N/Ti) ratio of the nitrogen-rich TiN hard mask layer 110 is greater than 1.0. According to an embodiment of the present invention, the N/Ti ratio of the entire nitrogen-rich TiN hard mask layer 110 is greater than 1.0. According to an embodiment of the present invention, for example, the N/Ti ratio of the nitrogen-rich TiN hard mask layer 110 may be between 1.0 and 1.2. According to an embodiment of the present invention, the N/Ti ratio of the nitrogen-rich TiN hard mask layer 110 is equal to or greater than 1.04.

[0037] According to an embodiment of the present invention, the nitrogen-rich TiN hard mask layer 110 may be formed by a physical vapor deposition (PVD) process such as sputtering, and the deposition conditions may include: DC power greater than 4000 W, for example, 7500 W-8500 W, argon/nitrogen (Ar/N.sub.2) gas flow ratio of 30/100, and deposition at room temperature.

[0038] The present invention utilizes high DC power to form a nitrogen-rich TiN hard mask layer 110 to control the nitrogen-to-titanium ratio between 1.0 and 1.2, which can reduce the electron capture in the p-GaN gate layer during the operation of the GaN-based semiconductor device 1, thereby improving reliability of the GaN-based semiconductor device 1.

[0039] According to an embodiment of the present invention, the patterning of the p-GaN gate layer 108 and the nitrogen-rich TiN hard mask layer 110 can be accomplished by photolithography and dry etching.

[0040] According to an embodiment of the present invention, the GaN-based semiconductor device 1 further includes a gate electrode layer 120 disposed on the nitrogen-rich TiN hard mask layer 110. According to an embodiment of the present invention, for example, the gate electrode layer 120 may include a TiN bottom layer 120, an AlCu middle layer 124 and a TiN top layer 126. According to an embodiment of the present invention, the TiN bottom layer 122 is in direct contact with the nitrogen-rich TiN hard mask layer 110, and the TiN bottom layer 122 may slightly recess into the upper surface of the nitrogen-rich TiN hard mask layer 110.

[0041] According to an embodiment of the present invention, the GaN-based semiconductor device 1 further includes an Al.sub.2O.sub.3 passivation layer 111 covering the sidewalls of the p-GaN gate layer 108, the sidewalls of the nitrogen-rich TiN hard mask layer 110 and the top surface of the AlGaN layer 106.

[0042] According to an embodiment of the present invention, the GaN-based semiconductor device 1 further includes an insulating layer 112, such as a tetraethoxysilane (TEOS) silicon oxide layer, disposed on the Al.sub.2O.sub.3 passivation layer 111. According to an embodiment of the present invention, an opening 112a is formed in the insulating layer 112 and the Al.sub.2O.sub.3 passivation layer 111, and the gate electrode layer 120 is filled into the opening 112a, so that the gate electrode layer 120 is electrically connected to the nitrogen-rich TiN hard mask layer 110.

[0043] Please also refer to FIG. 2, which is a flow chart of the manufacturing method of the GaN-based semiconductor device 1, wherein like layers, regions or elements are still designated by like numeral numbers or labels. As shown in FIG. 2, in Step 21, a substrate 100 is provided. A buffer layer 102, a GaN channel layer 104, an AlGaN layer 106 and a p-GaN gate layer 108 are sequentially formed on the substrate 100.

[0044] According to an embodiment of the present invention, the buffer layer 102 may include AlN or GaN, and the thickness of the buffer layer 102 is, for example, 3-5 m. According to an embodiment of the present invention, the thickness of the GaN channel layer 104 is, for example, 200-400 nm, the thickness of the AlGaN layer 106 is, for example, 10-14 nm, and the thickness of the p-GaN gate layer 108 is, for example, 60-100 nm.

[0045] In step 22, a physical vapor deposition (PVD) process is performed to form a nitrogen-rich TiN hard mask layer 110 on the p-GaN gate layer 108 under a DC power greater than 4000 W, for example, a DC power of 7500-8500 W, wherein the nitrogen-to-titanium ratio of the nitrogen-rich TiN hard mask layer 110 is greater than 1.0. According to an embodiment of the present invention, the nitrogen-to-titanium ratio of the nitrogen-rich TiN hard mask layer 110 is equal to or greater than 1.04.

[0046] In Step 23, a photolithography process and a dry etching process are performed to pattern the nitrogen-rich TiN hard mask layer 110 and the p-GaN gate layer 108.

[0047] In Step 24, an Al.sub.2O.sub.3 passivation layer 111 is deposited to conformally cover the top surface and sidewalls of the p-GaN gate layer 108, the sidewalls of the nitrogen-rich TiN hard mask layer 110 and the top surface of the AlGaN layer 106. Subsequently, an insulating layer 112 is formed on the Al.sub.2O.sub.3 passivation layer 111. According to an embodiment of the present invention, for example, the insulating layer 112 may include a tetraethoxysilane (TEOS) silicon oxide layer, but is not limited thereto.

[0048] In Step 25, a metallization process is performed. First, an opening 112a is formed in the insulating layer 112 and the Al.sub.2O.sub.3 passivation layer 111, so that the opening 112a exposes part of the upper surface of the nitrogen-rich TiN hard mask layer 110. A gate electrode layer 120 is then filled into the opening 112a and is electrically connected to the nitrogen-rich TiN hard mask layer 110.

[0049] According to an embodiment of the present invention, the gate electrode layer 120 may include a TiN bottom layer 122, an AlCu middle layer 124 and a TiN top layer 126, wherein the TiN bottom layer 122 is in direct contact with the nitrogen-rich TiN hard mask layer 110. Subsequent steps include fabrication of source and drain contacts, which are not described in detail because these steps are well-known techniques.

[0050] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.