In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A data storage structure is arranged over the substrate and laterally between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the data storage structure. The first doped region is laterally between the isolation structure and the data storage structure. A remnant is arranged over and along a sidewall of the isolation structure. The remnant includes a first material having a vertically extending segment and a horizontally extending segment protruding outward from a sidewall of the vertically extending segment.

Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.

Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.

Disclosed herein is A structure comprising: a top gate electrode and a bottom gate electrode, a channel layer formed from a channel material with a band gap modulable by electric field, the channel layer being electrically insulated from the top gate electrode and the bottom gate electrode and being located adjacent to at least one layer of a negative capacitance material.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

An anti-fuse device by ferroelectric characteristic is provided, which comprises an active area including a source region, a drain region laterally spaced from the source region and a channel between the source region and drain region, and a gate structure including a ferroelectric layer formed on the channel as well as a gate electrode formed on the ferroelectric layer. A programming operation of the anti-fuse device is performed by application of power to the gate electrode and at least one of the source region and drain region to cause a permanent electric field polarization in the ferroelectric layer to induce a conduction path along the channel. After the programming operation, the anti-fuse device will much easily turn on as the threshold voltage decreases even the operating voltage applied to the gate electrode is zero bias.

A semiconductor device has, in a gate insulating layer, in an XPS spectrum of O 1s obtained by an X-ray photoelectron spectroscopy (XPS) using a monochromatic aluminum K (1486.6 eV) source, a ratio (%) of an AlO peak observed in a binding energy of about 530.3 eV to about 531.6 eV to all peaks of greater than or equal to about 80%.

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

A device structure can be formed by forming a layer stack comprising a continuous bottom electrode material layer, a continuous dielectric layer, and a continuous dielectric metal oxide layer; increasing an oxygen-to-metal ratio in a top surface portion of the continuous dielectric metal oxide layer by incorporating oxygen atoms into the top surface portion of the continuous dielectric metal oxide layer; depositing a continuous semiconductor layer over the continuous dielectric metal oxide layer; and patterning the continuous semiconductor layer and the layer stack to form a patterned layer stack including a bottom electrode, a dielectric layer, a dielectric metal oxide layer, and a semiconductor layer.

A semiconductor memory device includes a semiconductor layer; a gate electrode; a first insulating film provided between the semiconductor layer and the gate electrode, and including at least one of oxygen, hafnium, or a first additive element; and a second insulating film provided between the first insulating film and the gate electrode. The first insulating film includes a first additive region, a second additive region provided between the first additive region and the gate electrode, and a memory region provided between the first additive region and the second additive region. The first additive region includes a second additive element selected from a group consisting of ruthenium, titanium, molybdenum, tantalum, tungsten, platinum, and combinations thereof. The second additive region includes a third additive element selected group consisting of ruthenium, titanium, molybdenum, tantalum, tungsten, platinum, and combinations thereof.