This semiconductor device comprises a semiconductor substrate of a first conductivity type, a semiconductor layer of the first conductivity type, a first electrode, a second electrode, a first trench, a second trench, an insulating layer, a third electrode, and a well region of a second conductivity type. The well region includes a first region that is adjacent to the first trench, a second region that is adjacent to the second trench, and a third region that is located between the first region and the second region in a second direction. The impurity concentration of the first region and the impurity concentration of the second region are both lower than the impurity concentration of the third region.

A molding is formed by laminating an aggregate of SiC and a paste containing Si and C powders on an epitaxial layer of SiC formed on a support substrate of SiC to form an intermediate sintered body in which polycrystalline SiC is produced from the Si and C powders by reaction sintering, free Si is carbonized to SiC to form a sintered body layer, and the support substrate is removed from the epitaxial layer to form a semiconductor substrate in which the epitaxial layer and the sintered body layer are laminated.

A power device includes a substrate, a drift layer disposed on the substrate, a terminal region and an active region disposed in the drift layer, an electrode layer disposed on the active region, a Schottky contact layer disposed between the electrode layer and the active region, a passivation layer disposed on the drift layer, and an isolation layer disposed between the passivation layer and the electrode layer so that the passivation layer and the electrode layer are at least partially separated from each other. The isolation layer, the electrode layer, and the passivation layer each respectively has a thermal expansion coefficient a, b, c, and a>b>c.

A merged PiN Schottky (MPS) diode includes a substrate, a first epitaxial layer of a first conductivity type, doped regions of a second conductivity type, a second epitaxial layer of the first conductivity type, and a Schottky metal layer. The first epitaxial layer is disposed on the first surface of the substrate. The doped regions are disposed in a surface of the first epitaxial layer, wherein the doped regions consist of first portions and second portions, the first portions are electrically floating, and the second portions are electrically connected to a top metal. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein trenches are formed in the second epitaxial layer to expose the second portions of the doped regions. The Schottky metal layer is conformally deposited on the second epitaxial layer and the exposed second portions of the doped regions.

A method for forming an ohmic contact on a semiconductor component, for example a high-power electrical diode, is provided. An example method includes depositing a first metal layer on a top surface of a semiconductor drift layer having an electrical contact point, the first metal layer highly reflective of a laser light. The method further includes depositing a second metal layer on portions of the first metal layer aligned with the electrical contact point, the second metal layer selected to absorb the laser light. The method further includes exposing the first and the second metal layers to the laser light in a laser annealing process, causing the second metal layer to substantially increase in temperature due to the laser light. The increase in temperature of the second metal layer causing the ohmic contact to form between the electrical contact point and the first metal layer.

The present application discloses a Schottky barrier diode device and a manufacturing method therefor. The Schottky barrier diode device comprises an epitaxial wafer having an epitaxial layer. The epitaxial layer comprising a first surface and a second surface that are opposite to each other, and the first surface being provided with a functional region and trench regions located on both sides of the functional region; multi-level trenches located in the trench regions, each of the multi-level trenches comprising: multiple sub-trenches, the multiple sub-trenches successively comprising a first-level sub-trench to an Nth-level sub-trench in a first direction; the width of the sub-trenches in the same multi-level trench being sequentially increased in the first direction. The side wall of at least the first-level sub-trench being provided with a side wall protection structure.

A semiconductor device includes a chip having a principal surface, a pn-junction portion extending in a horizontal direction along the principal surface inside the chip, a trench insulating structure formed in the principal surface such that the trench insulating structure penetrates through the pn-junction portion, and demarcating a diode region in the chip, a barrier forming region formed in a surface layer portion of the principal surface in the diode region, and a metal layer located on the principal surface such that the metal layer covers the barrier forming region in the diode region, and forming a Schottky-junction portion with the barrier forming region.

A semiconductor rectifier device includes: an epitaxial layer, having a top surface and a bottom surface; a first doped region having a first conductivity type, located in the epitaxial layer; a first trench structure, located in the first doped region; a second trench structure adjacent to the first trench structure, located in the first doped region; a second doped region having a second conductivity type, located in the epitaxial layer between the first trench structure and the second trench structure, wherein a depth of the second doped region is less than a depth of the first trench structure; and a metal layer, located on the top surface of the epitaxial layer, covering the first trench structure, the second trench structure, and the second doped region, wherein the metal layer is in contact with the top surface, forming a Schottky interface.

A method for forming a graphene layer on a semiconductor substrate, a semiconductor diode utilizing the method for graphene layer formation, and an optoelectronic semiconductor device also utilizing the method for graphene layer formation are provided. An example method for disposing a graphene layer on a semiconductor substrate may include depositing a metal catalyst layer on a top surface of the semiconductor substrate and patterning the metal catalyst layer, such that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures. The method may further include facilitating a graphene growth process on an exposed surface of the one or more metal catalyst layer structures, wherein the graphene growth process forms the graphene layer on the exposed surfaces of the one or more metal catalyst layer structures.

A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500 C. and 2600 C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.