A semiconductor substrate includes a p-type substrate body, an n-type buried layer on the p-type substrate body, and a p-type semiconductor layer on the n-type buried layer. A DTI region penetrates through the p-type semiconductor layer and the n-type buried layer, and reaches the p-type substrate body. An n-type semiconductor region, which is a cathode region of a Zener diode, and a p-type anode region of the Zener diode are formed in the semiconductor layer. The p-type anode region includes a p-type first semiconductor region formed under the n-type semiconductor region, and a p-type second semiconductor region formed under the p-type first semiconductor region. A PN junction is formed between the p-type first semiconductor region and the n-type semiconductor region. An impurity concentration of the p-type second semiconductor region is higher than an impurity concentration of the p-type first semiconductor region.

A semiconductor device includes a first well region, a second well region, a body region, and a cathode region. The impurity concentration of the body region is higher than the impurity concentration of the first well region, and the impurity concentration of the second well region is higher than the impurity concentration of the body region. In plan view, the body region includes the cathode region, and the cathode region includes the second well region. The cathode region configures a cathode of a Zener diode, and the first well region, the second well region, and the body region configure an anode of the Zener diode.

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes.

A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.

Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region having a second conductivity type, wherein the first semiconductor region separates the second semiconductor region from the substrate. In one embodiment, the substrate and the first semiconductor region have U-shaped boundary. In a further embodiment, the first semiconductor region comprises an alloy of a first material and a second material, where the concentration of the second material varies from a maximum to a minimum, where the first semiconductor region adjacent to the second semiconductor region has the minimum of the concentration of the second material.

The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

A light emitting device package can include a sub-mount having a first surface, a second surface, a bottom surface and a cavity; a first layer on the first surface; a second layer on the second surface; a third layer on the bottom surface; a light emitting device on the first layer and including a supporting layer including an anti-diffusion layer, a first electrode on the supporting layer, a semiconductor light emitting structure electrically connected to the first electrode, and a second electrode electrically connected to the semiconductor light emitting structure, in which the first and second electrodes electrically connect to the first layer and the second layer, respectively, and the semiconductor light emitting structure includes a light extraction structure; an ESD property improving diode on the second surface, electrically connected to the second layer and arranged a distance apart from the light emitting device, and a lens on the sub-mount.

In accordance with an embodiment, semiconductor component includes a compound semiconductor material based semiconductor device coupled to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.

An electrostatic discharge protection device includes first and second diodes series-connected between first and second connection terminals. A third connection terminal is coupled to a junction of the first and second diodes. A capacitor is connected in parallel with the first and second diodes between the first and second terminals.

A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.