A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes first to fifth circuits. Each of the first to fourth circuits includes first and second cells, a sixth circuit, first and second current generation circuits, a first input terminal, and a second output terminal. The first circuit to the fourth circuit are electrically connected to each other in a ring, and the first circuit is electrically connected to the fifth circuit. In each of the first to fourth circuits, the first cell is electrically connected to the second cell through the first wiring, the first current generation circuit, and the third wiring, and is electrically connected to the first input terminal and the sixth circuit through the second wiring. The second cell is electrically connected to the first output terminal through the second current generation circuit. Note that the first current generation circuit functions as a current mirror circuit, and the second current generation circuit functions as an arithmetic circuit of a function system. The first cell performs an arithmetic operation of a product, and the second cell retains the result of the arithmetic operation.

A power module has a first layer, a second layer, and an inductor assembly. The first layer has a plurality of connecting pillars, a first plurality of capacitors electrically connected in parallel between an input node and a reference ground, and a second plurality of capacitors electrically connected in parallel between an output node and the reference ground. The second layer is attached between the first layer and the inductor assembly, having a first pair of switches forming a first switch node, and a second pair of switches forming a second switch node. The first pair of switches and the second pair of switches are electrically connected between the input node and the reference ground. The inductor assembly has a first inductor electrically connected between the output node and the first switch node and a second inductor electrically connected between the output node and the second switch node.

A capacitor structure includes a base substrate, a through via extending in a vertical direction from a top surface of the base substrate to a bottom surface of the base substrate, a first sub-capacitor structure disposed on the bottom surface of the base substrate and including a first lower electrode electrically connected to a first end of the through via, a first upper electrode, and a first capacitor dielectric layer between the first lower electrode and the first upper electrode, and a second sub-capacitor structure disposed on the top surface of the base substrate and including a second lower electrode electrically connected to a second end, opposite to the first end, of the through via, a second upper electrode, and a second capacitor dielectric layer between the second lower electrode and the second upper electrode on the top surface of the base substrate.

A semiconductor structure including a substrate and a capacitor is provided. The capacitor is located on the substrate. The capacitor includes a first electrode, a second electrode, a first dielectric layer, and a second dielectric layer. The first electrode is located on the substrate. The first electrode has a first surface and a second surface opposite to each other. The second electrode is located on the first electrode. The first dielectric layer is located between the first surface and the second electrode. The second dielectric layer is located between the first dielectric layer and the second electrode and between the second surface and the second electrode.

The present disclosure discloses a package including a first support portion, a second support portion, and multiple pins. The first support portion includes a first upper metal layer and a first lower metal layer, wherein the first lower metal layer is connected to and overlaps with the first upper metal layer, corresponding to the position of the first upper metal layer. The second support portion is laterally separated from the first support portion, and the second support portion includes a second metal layer. The multiple pins are laterally separated from the first support portion and the second support portion, where in a top view, a ratio of a maximum length of the second metal layer to a maximum length of the package is greater than .

An electronic module, including: a first conductive plate which contains copper or a first copper alloy as a main component thereof; a second conductive plate which has a main surface that faces the first conductive plate and has a side surface that extends continuously from the main surface, and which contains copper or a second copper alloy as a main component thereof; and a first metal oxide layer which is provided on the main surface and the side surface of the second conductive plate, and which contains a first metal oxide that is of a metal different from a metal of the second conductive plate and is electrically insulating.

A semiconductor structure and a method of fabricating the structure are disclosed. The semiconductor structure includes a substrate, a device layer disposed on the substrate, a power line disposed on the device layer, a first capacitor circuit, a second capacitor circuit, and a control circuit disposed on the power line and configured to control the first capacitor circuit. The first capacitor circuit includes a first conductive via disposed on the power line, a first conductive line disposed on the first conductive via and aligned to a first side of the power line, and a first trench capacitor disposed on the first conductive line. The second capacitor circuit includes a second conductive via disposed on the power line, a second conductive line disposed on the second conductive via and aligned to a second side of the power line, and a second trench capacitor disposed on the second conductive line.

A method of manufacturing a 3D device including: forming a first level including first transistors and a first interconnect; forming a second level including second transistors; overlaying the second level on the first level; and bonding the second level to the first level; the bonding includes performing metal region to metal region bonding, the 3D device includes at least four electronic circuits (AL4ECs) and at least one redundancy circuit, where the AL4ECs each include a first circuit which includes a portion of the first transistors, where the AL4ECs include a second circuit which includes a portion of the second transistors, where the AL4ECs each include a vertical connectivity structure (VCSt), the VCSt includes pillars, where the pillars are configured to provide electrical connections between the first circuit and the second circuit, and where the AL4ECs each include at least one memory control circuit and at least one memory array.

A semiconductor module includes a cooler, a plurality of semiconductor devices, and a capacitor. The cooler includes a housing having a receiving portion and a hollow portion that is disposed externally around the receiving portion as viewed in a first direction. The housing has a first surface, a second surface, and a third surface on which the plurality of semiconductor devices are respectively mounted. Each of the first surface, the second surface, and the third surface faces away from the receiving portion with respect to the hollow portion in a direction orthogonal to the first direction. The first surface, the second surface and the third surface each have a different normal direction. At least a part of the capacitor is housed in the receiving portion.

The present invention provides a semiconductor device and a method of fabricating the device, in which in each adjacent pair of semiconductor substrates, a first semiconductor substrate is bonded to a backside of a second semiconductor substrate, and external connection terminals are adjacent, and electrically connected, to a second semiconductor substrate. In each adjacent pair of semiconductor substrates, there is a first dielectric layer containing plug structures, which electrically connect the semiconductor substrates to each other. With this arrangement, power from an external power source can be supplied to each semiconductor substrate through a power transmission path constructed of plug structures. At least some first dielectric layers each contain a DTC structure, which is electrically connected to second ends of the plug structures in specific first dielectric layer. During propagation of an electrical signal through the plug structures, it passes through the DTC structure before arriving at downstream semiconductor substrate.