A semiconductor device includes: one or more semiconductor modules arranged in a row; a pair of cooling members disposed so as to sandwich the semiconductor modules and configured to cool the semiconductor modules; a pair of sandwiching members each disposed on an opposite side of the semiconductor module across a corresponding one of the pair of cooling members to oppose the corresponding one of the pair of cooling members; and a coupling portion that couples a pair of sandwiching members to each other and presses each of the pair of sandwiching members against the opposing one of the cooling members, in which at least one of the pair of sandwiching members includes a plurality of support portions disposed to oppose ends of the arranged semiconductor modules and a space between the semiconductor modules, and a spring portion extending from each of the plurality of support portions in an arrangement direction of the semiconductor modules and abutting the cooling member, and the coupling portion couples the support portion provided to the one of the pair of sandwiching members and another sandwiching member.

Thermal resistance of a sintered metal joining section is reduced to cope with an increase in the area of a chip size and layer thinning of the semiconductor chip. A sintered metal layer joins the semiconductor chip to a wiring layer and the wiring layer has a trench extending from the semiconductor chip mounting region where the semiconductor chip is mounted to the outside of the semiconductor chip mounting region. The sintered metal layer is formed in the trench and to the outside of the upper end of the trench and in the trench formed to the outside of the semiconductor chip mounting region. The depth of the trench differs between the trench in the vicinity of the center of the semiconductor chip mounting region and the trench in the vicinity of the end portion of the semiconductor chip mounting region.

A power conversion device includes a power conversion unit and a control unit. The power conversion unit includes a first semiconductor module. The first semiconductor module includes a plurality of power semiconductor elements. Some of the plurality of power semiconductor elements are detection target elements. The power conversion unit further includes a temperature sensor and a voltage sensor. The temperature sensor detects a surface temperature of the detection target element as a sensor position temperature. The voltage sensor detects an inter-terminal voltage of the detection target element. The control unit calculates a loss in the detection target element based on the sensor position temperature and the inter-terminal voltage, and estimates a maximum temperature based on the calculated loss.

A bypass diode assembly and a method for fabricating the bypass diode assembly are provided, the bypass diode assembly comprising an electrically insulating tape, an electrically conductive ribbon extending over the back side of the tape and locally exposed at the front side of the tape through an opening, a semiconductor component positioned in a hole through the tape, wherein the semiconductor component comprises a diode electrically connected between a first contact pad of the semiconductor component in electrical contact with the electrically conductive ribbon and a second contact pad of the semiconductor component, and an electrically conductive ribbon portion on the front side of the tape in electrical contact with the second contact pad of the semiconductor component. The electrically conductive ribbon portion is electrically isolated from the first electrically conductive ribbon by the electrically insulating tape. A photovoltaic module comprising at least one bypass diode assembly is provided.

The invention provides an electronic cascode power device. The electronic cascode power device has a high-side terminal, a low-side terminal and a control terminal. The electronic cascode power device comprises: a high-voltage silicon (Si) super-junction MOSFET with a drain connected to the high-side terminal of the cascode device; a low-voltage gallium nitride (GaN) HEMT with a drain connected to a source of the high-voltage Si super-junction MOSFET, a source connected to the low-side terminal of the cascode device and a gate connected to the control terminal of the cascode device; and an overvoltage clamping circuit connected between the drain and source of the low-voltage GaN HEMT. The provided cascode structure can effectively suppress the reverse-recovery process of super-junction MOSFET, achieving nearly 50% reduction in overall switching loss at high current levels.

A power semiconductor module arrangement includes a housing, a substrate arranged in or forming a bottom of the housing, a bus bar electrically coupled to the substrate and having opposite first and second ends, and a pressing element. The first end of the bus bar is electrically and mechanically coupled to the substrate, and the second end extends to the outside of the housing. The second end of the bus bar extends in a horizontal plane in parallel to the substrate and has an opening extending therethrough in a vertical direction perpendicular to the horizontal plane. The pressing element is arranged directly adjacent to a surface of the second end of the bus bar facing towards the substrate. The pressing element includes a screw nut aligned with the opening extending through the second end of the bus bar, and one or more projecting sectors extending horizontally from the screw nut.

A semiconductor device includes a plurality of transistors electrically connected in parallel to each other, each of the plurality of transistors including a first pad; and a conductive member. The first pad is a source pad or an emitter pad. The first pad includes a first connection region; and a second connection region and a third connection region, the first connection region being located between the second connection region and the third connection region. The semiconductor device includes a first connection member that connects the first connection region to the conductive member; a second connection member that connects second connection regions of two transistors among the plurality of transistors; and a third connection member that connects third connection regions of the two transistors among the plurality of transistors.

A package and method is disclosed. In one example, the package includes a carrier comprising a component mounting area from which a lateral extension extends, the lateral extension being configured for being clamped by an encapsulant tool pin during encapsulation, an electronic component mounted on the component mounting area, and an encapsulant encapsulating at least part of the electronic component and part of the carrier. The lateral extension is laterally retracted with respect to a neighboring vertical sidewall of the encapsulant. The encapsulant laterally covers the lateral extension.

The present disclosure discloses a package including a first support portion, a second support portion, and multiple pins. The first support portion includes a first upper metal layer and a first lower metal layer, wherein the first lower metal layer is connected to and overlaps with the first upper metal layer, corresponding to the position of the first upper metal layer. The second support portion is laterally separated from the first support portion, and the second support portion includes a second metal layer. The multiple pins are laterally separated from the first support portion and the second support portion, where in a top view, a ratio of a maximum length of the second metal layer to a maximum length of the package is greater than .

A logic die for performing a through silicon via (TSV) repair operation and a semiconductor device including the logic die are provided. The semiconductor device includes the logic die including a memory controller and an interface circuit, a plurality of core dies stacked in a vertical direction on the logic die, each of the plurality of core dies including a memory cell array, and a plurality of through silicon vias (TSVs) configured to electrically connect the logic die to the plurality of core dies, the plurality of TSVs including a plurality of operation TSVs and at least one redundancy TSV. The interface circuit includes a plurality of TSV circuit blocks electrically connected to the plurality of TSVs, respectively, and a TSV repair logic configured to perform a repair operation on a first TSV, in which a defect occurs and a first TSV circuit block, electrically connected to the first TSV.