A semiconductor package according to an embodiment includes an first insulating layer; a first pad disposed on the first insulating layer; and a first protective layer disposed on the first insulating layer and having a first through hole vertically overlapping the first pad, wherein an inner wall of the first through hole includes a contact surface in contact with a side surface of the first pad, and a non-contact surface located on the contact surface, and wherein a ratio of a thickness of the contact surface to a thickness of the first pad is 1:2 or more and less than 1:1.

A semiconductor package includes an interposer, a redistribution layer chip, and a semiconductor element. The redistribution layer chip includes a redistribution element having a surface overlapping the semiconductor element and a first mold resin layer mounted to an opposite surface of the redistribution element and containing resin. The opposite surface is opposite the surface of the redistribution element overlapping the semiconductor element. The redistribution element includes an insulating layer having an insulation property and a first redistribution layer covered by the insulating layer. The first redistribution layer includes a first conductive portion at least partly located on the surface of the redistribution element overlapping the semiconductor element. The interposer includes a second redistribution layer including a second conductive portion located on a surface of the interposer overlapping the semiconductor element. The semiconductor element is electrically connected to the first conductive portion and the second conductive portion.

This power conversion device comprises a plurality of circuit bodies, a wiring board, and a smoothing capacitor, wherein: the wiring board has a plurality of stacked wiring parts to which the plurality of circuit bodies and the plurality of smoothing capacitors are respectively connected; and inter-phase wiring parts respectively formed between the plurality of stacked wiring parts; in the stacked wiring parts, positive electrode wires and negative electrode wires are stacked to overlap each other; in the inter-phase wiring parts, a plurality of the positive electrode wires and a plurality of the negative electrode wires are stacked to be separated from each other on a plane of the wiring board; and the inter-phase wiring parts have a via passing therethrough in the thickness direction of the wiring board.

This power conversion device comprises a plurality of circuit bodies, a wiring board, and a smoothing capacitor, wherein: the wiring board has a plurality of stacked wiring parts to which the plurality of circuit bodies and the plurality of smoothing capacitors are respectively connected; and inter-phase wiring parts respectively formed between the plurality of stacked wiring parts; in the stacked wiring parts, positive electrode wires and negative electrode wires are stacked to overlap each other; in the inter-phase wiring parts, a plurality of the positive electrode wires and a plurality of the negative electrode wires are stacked to be separated from each other on a plane of the wiring board; and the inter-phase wiring parts have a via passing therethrough in the thickness direction of the wiring board.

A micromechanical component and a corresponding production method. The micromechanical component is equipped with a substrate, a function chip which is attached to the substrate and has a main surface facing away from the substrate, wherein one or more bond pads are provided on the main surface, which are bonded to the substrate by a respective bond wire. On the main surface or above the main surface of the function chip, a cover chip, which is formed from a chip material that has a diffusion-inhibiting effect on halogen ions located in the mold compound, is attached as a diffusion barrier to a mold package. The cover chip covers the main surface substantially completely. The micromechanical component further includes the mold package, in which the function chip is packaged together with the cover chip.

A chip package structure includes a substrate, a chip, and a shielding layer. The substrate includes a plurality of stacked metal layers. A first conductive column runs through at least two metal layers, and has a first contact surface that is exposed to an outer side of the substrate and that faces a top surface of the substrate. The chip is disposed on the top surface of the substrate. The shielding layer is formed outside the chip, and is connected to the first conductive column through the first contact surface, and the shielding layer is grounded. In the chip package structure, the shielding layer is connected to the first conductive column through contact with the first contact surface, and is grounded to form an electromagnetic shielding cavity.

This disclosure provides a chip package structure, an electronic device, and a packaging method of the chip package structure, and relate to the field of chip packaging technologies, to reduce impact of a through-silicon via (TSV) on performance of an electronic component. The chip package structure may include a first component chip, a support chip, and a second component chip. The second component chip is stacked on the support chip through a bonding layer, and the first component chip is disposed on a side that is of the second component chip and that is away from the support chip. A conductive channel penetrates the support chip and the second component chip. The support chip includes a first substrate, and the second component chip includes a second substrate and an electronic component layer formed on the second substrate.

A semiconductor die included in a semiconductor die package may include a plurality of decoupling trench capacitor regions in a device region of the semiconductor die. At least two or more of the decoupling trench capacitor regions include decoupling trench capacitor structures having different depths. The depths of the decoupling trench capacitor structures in the decoupling trench capacitor regions may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for circuits of the semiconductor die package, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package.

As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks. Alternatively, source side select gate electrical isolation is implemented using ion implantation on the source select gates to raise threshold voltages on different subsets.

As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks. Alternatively, source side select gate electrical isolation is implemented using ion implantation on the source select gates to raise threshold voltages on different subsets.